International Journal of Scientific & Engineering Research, Volume 4, Issue 12, December-2013 1832 ISSN 2229-5518 IJSER © 2013 http://www.ijser.org AN FPGA IMPLEMENTATION BELIEF PROPAGATION DECODING ALGORITHM M. M. Jadhav 1 , Chetna N. Kharkar 2 , Dr. A. M. Sapkal 3 Abstract — Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices. In this paper we have presented an FPGA based self error checking & correction system with higher capability. We implemented the error correction algorithms such as belief propagation & bit flip algorithm. The number of error corrected is simulated using Xilinx High level Synthesis tool & Modelsim simulator. A complete self checking system is implemented on Xilinx Spartan 3E FPGA & synthesis is done using ISE13.2. The decoded codeword of the decoder is displayed on PC HyperTerminal using serial Rs232 interface. The system is capable of correcting large & different size of codeword. Self error detection & correction capability of the system is compared & verified in presence of noise. Index Terms — LDPC codes, LDPC decoder, FPGA Implementation, bit flip decoding, Belief Propagation, log domain, soft decoding, hard decoding ——————————  ————————— 1. INTRODUCTION Low-density parity-check (LDPC) codes are forward error-correction codes [1], first proposed in the 1962 PhD thesis of Gallager at MIT[2].The computational effort in implementing coder & encoder are more for these codes.LDPC codes is then rediscovered by Mackay and Neal [3].These codes are decoded iteratively by Belief propagation decoding on their associated factor graph [4]. In the mean time the field of forward error correction was dominated by highly structured algebraic block and convolution codes. _______________________________________ 1 M. M. Jadhav is presently perusing PHD from Government college of Engineering, Pune in the field of communication. He has guided graduates & more than ten Post graduates students, His area of Interest is communication system .Email- makj123@yahoo.com 2 Chetna N. Kharkar is Currently Working as a Sr. Design Engineer at Qualitat systems, Pune (India).She has a 6+ years of experience in Embedded domain. Perusing Master of Engineering from Sinhgad college of Engineering,Pune,India,Email-chetnakharkar@gmail.com 3 Dr. A. M. Sapkal is HOD of E&TC Department at government college of Engineering, Pune.He has 23 years of experience in teaching, 3 years Industrial & 14 years of Research experience. He has guided More than 100 post graduates students. Email -hod.extc@coep.ac.in Optimization results for various channels, such as the Additive White Gaussian Noise (AWGN) channel and the Binary Symmetric Channel (BSC) have produced specific degree distributions such that the corresponding codes come very close to capacity [5].In fact, the state of art in the coding field is currently achieved by LDPC codes, which was accomplished by Chung et al. [6].It was soon recognized that these block codes were in fact a rediscovery of the LDPC codes developed years earlier by Gallager. New generalizations of Gallager’s LDPC codes by a number of researchers produced new irregular LDPC codes. These codes easily outperform the best turbo codes, as well as offering certain practical advantages and cleaner setup for theoretical results. Today, design techniques for LDPC codes exist which enable the construction of codes which approach the Shannon’s capacity to within hundredths of a decibel. Low density parity check (LDPC) codes have been extensively adopted in next-generation forward error correction applications. They achieve very good performance using the iterative decoding approach of the belief-propagation (BP) [7].The main contribution of this paper is implementation of self error checking system on Xilinx Spartan 3E FPGA using High level synthesis tool and Synthesis has been done for LDPC codes Construction & Bit-flipping decoding. Self error checking system is flexible to IJSER