FASTNR:An Efficient Fault Simulator for Linear and Nonlinear OC Circuits J. Soares Augusto and C. F. Beltran Almeida INESCIIST, Aptd. 13069, 1000 Lisboa, Portugal. E-mail: jasa@dalton.inesc.ptandcfb@dalton.inesc.pt Abstract In this paper we describe the simulator FASTNR (FAST Newton-Raphson) where an efficient methodology for solving the faulty circuit equations, called FAult RUBber Stamps (FARUBS), is implemented. Its application to single fault simulation in linear and nonlinear circuits is reported. The efficient fault simulation in nonlinear DC circuits is due both to the development of original linearized Newton-Raphson models for electronic devices and to the simulation of fault values in a "continuation" stream. Fault simulation in linear cascades with up to 5000 nodes has shown an improvement of four orders of magnitude in simulation time, when compared to that of the nominal circuit. In nonlinear circuits, the time efficiency is sometimes better than two orders of magnitude. Keywords: Efficient Analog Fault Simulation; Solution of Linear and Nonlinear Circuits; Analog Test and Diagnosis. 1. INTRODUCTION Efficient fault simulation is an important issue when Simulation-Before-Test (SBT) dictionary-based techniques are used in fault diagnosis of electronic circuits. A survey of efficient fault simulation in analog circuits is given in [1, 2, 3]. In this paper, we describe some results of single fault simulation with the FASTNR simulator [4], built around the modified Newton-Raphson (NR) algorithm, that implements a methodology calledfault rubber stamps for inserting faults in the circuit equations [3]. After a very concise (due to space limitations) survey of the literature on efficient fault simulation, we present the FARUBS methodology applied to linear circuits, and then we extend it to efficient fault simulation in nonlinear circuits. Several examples, including The original version of this chapter was revised: The copyright line was incorrect. This has been corrected. The Erratum to this chapter is available at DOI: © IFIP International Federation for Information Processing 2000 L. M. Silveira et al. (eds.), VLSI: Systems on a Chip 10.1007/978-0-387-35498-9_57