IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 9, SEPTEMBER 2013 2375 Fixed-Width Multipliers and Multipliers- Accumulators With Min-Max Approximation Error Davide De Caro, Senior Member, IEEE, Nicola Petra, Member, IEEE, Antonio Giuseppe Maria Strollo, Senior Member, IEEE, Fabio Tessitore, and Ettore Napoli Abstract—Fixed-width multipliers have two n-bits operands and produce an approximate n-bits results for their product. These multipliers discard part of the partial products matrix, to reduce hardware cost, and employ extra correction functions to reduce ap- proximation error. While previous papers mainly focus on average error metrics (like mean-square error), we present an in-depth analysis of the maximum absolute error (MAE) of these circuits. The MAE is the main parameter to be considered in important applications, like function evaluation. We describe an efficient numerical method to compute the MAE in fixed-width multipliers and fixed-width multiplier-accumulator (MAC) circuits. Further we present a technique to compute a com- pensation function, that can be efficiently implemented in hard- ware, aimed to minimize the MAE. The novel fixed-width multi- plier topologies proposed in the paper exhibit a MAE that is better than previously proposed solutions and that is close to the theoret- ical lower bound. As a practical application we employ the developed MAC with minimum MAE for the hardware computation of elementary func- tions, using piecewise linear approximation. Implementation results in a 65 nm technology and comparison with previously proposed architectures show that the topologies proposed in this paper allow reducing the MAE without worsening the electrical performances. Index Terms—Digital arithmetic, error analysis, error compen- sation, fixed-width multipliers, min-max approximation, multipli- cation. I. INTRODUCTION P ARALLEL multipliers are key elements in several dig- ital signal processing applications, such as filtering, con- volution, fast Fourier or discrete cosine transform, compression, hardware implementation of mathematical functions and so on. Thus, multiplier optimization in terms of area, power and speed is a major concern for digital designers. A conventional binary multiplier (full-width multiplier) pro- duces an output whose number of bit is doubled with respect to the input operands. In many applications, in order to avoid data path widening, it is necessary to compute the multiplication re- sult with the same bit width as the inputs. The simplest way to obtain this goal uses a full-width multiplier, whose output is rounded to bits. This gives the most accurate result for the bits output, with a hardware complexity, however, equal to the one of a full-width multiplier. Manuscript received March 16, 2012; revised November 05, 2012; accepted December 24, 2012. Date of publication February 22, 2013; date of current ver- sion August 26, 2013. This paper was recommended by Associate Editor M.-D. Shieh. The authors are with the Department of Electronic and Telecommunication Engineering, University of Napoli Federico II, Naples, Italy (e-mail: dade- caro@unina.it). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCSI.2013.2245252 In the last years, several approaches have been developed which trade accuracy for speed and power by discarding parts of the partial products matrix of the multiplier. In most cases the approximation error caused by the discarded terms is mitigated employing extra correction circuits. These circuits are denoted in Literature as fixed-width multipliers [1]–[31]. Fixed width multipliers lead to two sources of error: reduc- tion error and rounding error. Reduction error is due to the par- tial products that are not formed to save hardware. Rounding error occurs because the output of the multiplier is calculated with -bits precision. The correction circuits are employed to compensate for these two sources of error. Many error compensation methods have been proposed in the past. In the simplest techniques, rounding and reduction errors are compensated with a fixed bias [1]–[4]. Better accuracy is ob- tained by using so-called adaptive techniques [5]–[31], where a variable correction is employed to reduce the output error. In the majority of the published approaches the correction circuit is obtained from statistical consideration. The effect of discarded partial products is estimated by making some assumptions on multiplier inputs (that are almost always assumed to be inde- pendent and uniformly distributed) and by observing a small subset of retained partial products. This subset of observed par- tial products is named “input correction vector”, or , in the following, while the result of the correction circuit is indicated as the “compensation function”, . Statistical approaches are very useful when the error metric of interest is an average quantity, such as the mean square error or the mean error, since the statistical properties of dropped partial products can be estimated from the behavior of the . For in- stance, analytically derived are presented in [15] and in [19] while heuristics techniques are exploited in [11]–[14], [16]. In several applications, such as function evaluation [32]–[35], the maximum absolute error is the error metric to be considered. In these cases, the computational accuracy of every hardware component, including multipliers, is accurately con- trolled so that the total computation error meets the final target precision. Unfortunately, the is not an average quantity but instead it depends on the point-by-point behavior of the mul- tiplier, making the analysis much more difficult. The very com- putation of the of a truncated multiplier is a challenging task, requiring an exhaustive brute-force simulation. This is fea- sible only for multipliers with a small bit width of the inputs (named in the following), since the computational complexity increases as . Analytical estimations of the can be found for truncated multiplier with fixed correction bias [27]. In [28] an analytical expression for the of a particular family of truncated multiplier is obtained, with the help of a conjecture that is not valid in general (it is valid only for the truncated multiplier of [19]). 1549-8328 © 2013 IEEE