PIERS ONLINE, VOL. 2, NO. 6, 2006 689 The Optimal Design of the LVDS Bus with High EMS K. Radkovsky 1 , M. Kaska 1 , Z. Motycka 1 P. Drexler 2 , T. Jirku 2 , Z. Szabo 2 , E. Kadlecova 2 , and P. Fiala 2 1 TES, Prazska 597, 674 01 Trebic Czech Republic 2 Department of Theoretical and Experimental Electrical Engineering Kolejni 2906/4, 61200 Brno, Czech Republic Abstract— The article deals with results which were obtained during the process of designing the LVDS (low voltage differential signal) bus. This bus is very resistant to interference from the environment and to spurious emission of electromagnetic waves. According to the concrete requirements we prepared a design of the LVDS by means of numerical methods. The design was realized and its parameters verified experimentally. The basic parameter of bus is its impedance Z = 100 Ω, up to frequency f 1 = 100 MHz of the first harmonic of rectangle signal. DOI: 10.2529/PIERS060901103255 1. INTRODUCTION The LVDS bus is used in many applications, especially in those requiring fast and reliable data transmission. The advantages of this bus are commonly known. In special cases, we need to use the LVDS transmission technology with great immunity to electromagnetic interference (EMI). The main problem of the design of this type of bus is how to find the optimal impedance matching with respect to production technology. Fig. 1 shows the obvious LVDS bus configuration which interconnects a set of functional blocks, for example plug-in cards. The high electromagnetic susceptibility (EMS) of the LVDS bus is required by relevant rules, valid for the system application in nuclear power plants. With respect to electromagnetic compati- bility (EMS) regulations the specific design of the high-EMS LVDS bus was implemented with the help of numerical analysis, as shown in Fig. 2. The total length of the bus is l = 265 mm. The design exploits a multi-layer configuration, including the ground layer ensuring the shielding. Figure 1: An example of the classical LVDS bus configuration. Figure 2: Details of the designed LVDS bus. The bus design exploits the multi-layer PCB technology. Due to the used multi-layer technology, some restrictions have to be considered, for example the thickness of microstrip lines or dielectric layers. Fig. 2 shows basic dimensions of the bus design — the microstrip line spacing (A, B, X ), the layer spacing (H 1 , H 2 ), the thickness of the microstrip and the ground layer (T ), the width of the microstrip line (W ) and the width of the reference microstrip line (W s ). The thickness of the microstrip and the ground layer is H = 35 µm. The electrode S in Fig. 2 is the reference electrode placed on both sides of the PCB. The symbols + and − stand for the pair of the differential transmission line. The basic scheme of the setup of the LVDS system is in Fig. 3. The setup includes