Phil. Trans. R. Soc. A (2010) 368, 3967–3981 doi:10.1098/rsta.2010.0150 Optimizing electronic standard cell libraries for variability tolerance through the nano-CMOS grid BY JAMES ALFRED WALKER 1, *, RICHARD SINNOTT 2 ,GORDON STEWART 2 , JAMES A. HILDER 1 AND ANDY M. TYRRELL 1 1 Intelligent Systems Group, Department of Electronics, University of York, Heslington, York YO10 5DD, UK 2 National e-Science Centre, Kelvin Building, University of Glasgow, Glasgow G12 8QQ, UK The project Meeting the Design Challenges of nano-CMOS Electronics (http://www. nanocmos.ac.uk) was funded by the Engineering and Physical Sciences Research Council to tackle the challenges facing the electronics industry caused by the decreasing scale of transistor devices, and the inherent variability that this exposes in devices and in the circuits and systems in which they are used. The project has developed a grid-based solution that supports the electronics design process, incorporating usage of large-scale high-performance computing (HPC) resources, data and metadata management and support for fine-grained security to protect commercially sensitive datasets. In this paper, we illustrate how the nano-CMOS (complementary metal oxide semiconductor) grid has been applied to optimize transistor dimensions within a standard cell library. The goal is to extract high-speed and low-power circuits which are more tolerant of the random fluctuations that will be prevalent in future technology nodes. Using statistically enhanced circuit simulation models based on three-dimensional atomistic device simulations, a genetic algorithm is presented that optimizes the device widths within a circuit using a multi-objective fitness function exploiting the nano-CMOS grid. The results show that the impact of threshold voltage variation can be reduced by optimizing transistor widths, and indicate that a similar method could be extended to the optimization of larger circuits. Keywords: optimization; intrinsic variability; CMOS; e-Science; grid 1. Introduction Fundamental to the continued growth of the semiconductor industry is Moore’s Law, which states that the number of transistors integrated on a chip will double every 2 years, owing to the shrinking of devices through advances in technology. Recently, the scale of devices has approached the level where the precise placement of individual dopant atoms will affect the output characteristics of a device. *Author for correspondence (jaw500@ohm.york.ac.uk). One contribution of 16 to a Theme Issue ‘e-Science: past, present and future I’. This journal is © 2010 The Royal Society 3967 Downloaded from https://royalsocietypublishing.org/ on 15 February 2022