Ling, Wang and Ho: zyxwvutsrqpo An Efficient Controller Scheme for MPEG-2 Video Decoder 45 1 zy AN EFFICIENT CONTROLLER SCHEME FOR MPEG-2 VIDEO DECODER zyx Nam Ling Currently visiting: Centre for Signal Processing, Nanyang Tech. University Nanyang Avenue, Singapore 639798, Singapore email: enling@ntu.edu.sg Computer Engineering Department, Santa Clara University Santa Clara, CA 95053, U.S.A. nling Q mailer.scu.edu Nien-Tsu Wang Computer Engineering Department, Santa Clara University Santa Clara, CA 95053, U.S.A. nwangQscudc.scu.edu Duan-Juat Ho School of EEE, Nanyang Tech. University Nanyang Avenue, Singapore 639798, Singapore email: ehdjwong Q ntu.edu.sg Abstract zyxwvutsrq A video decoder with an efficient block-level- pipeline controller scheme for MPEG-2 MP@ML is presented zyxwvutsr in this paper. The architecture in most of the reported literature for MPEG-2 MP@ML video uses a 64-bit bus and a complex bus arbitration scheme to communicate with external DRAM, display, and incoming FIFO. Our design imposes a certain order in the DRAM access by various processing units instead of allowing any processing unit within the decoder to request bus access arbitrarily. This efficient DRAM accessing order allows us to reduce bus width from 64 bits to zyxwvuts 32 bits, without significantly increasing embedded buffer sizes, and still meet the requirements for MPEG-2 MP@ML real-time decoding. The bus arbitration algorithm is also simple, allowing for a less complex controller design. 1. Introduction The MPEG-2 [1] decoder technology has received a lot of attention in multimedia applications (e.g., DVD players and set-top boxes for digital TV). However, due to the nature of inter- frame coding in the MPEG-2 algorithm and the relatively low speed accessing for traditional DRAMs, the decoder architecture in most of the reported literature (e.g. [2], [3], [4]) uses a 64-bit bus to communicate with the external DRAM, the display, and the incoming FIFO. Moreover, the controller is of medium complexity. A bus arbitration unit that uses priority assignment and polling to resolve conflicts on the bus is usually employed. In most reported literature (e.g. [2], [3], [4]), communication between processing unit and external DRAMs are usually performed on a macroblock (16x16 pixels) level. A 64-bit bus is therefore necessary to reduce the large data transfer delay. Long data transfer durations also delay functional blocks in the processing unit from accessing the bus [2], and thus a more complex bus arbitration scheme combining priority assignment and polling has been adopted to resolve conflicts on the bus. To overcome the problem described above, our low cost MPEG-2 decoding system uses a high performance single chip MPEG-2 decoder with a block (8x8 pixels) level pipeline controller scheme. Moreover, we also classify individual processes as either deterministic or stochastic. Our controller allocates DRAM accesses of deterministic processes according to a pre-determined schedule, and each time it only loads one or two reference blocks from the DRAM for the motion compensator. As a result, the peak bus bandwidth (Mbyte/s) can be lowered and the system bus width can be reduced from 64 bits to 32 bits. Additionally, the controller complexity is significantly simpler than most existing ones. Computation and I/O operation are also balanced to minimize the sizes of embedded buffers in the decoder. Clock frequency is chosen to be 27 MHz, a simple multiple of the video sampling rate, for low power application. Our architecture also employs 2 MByte SDRAMs running at 83 MHz to store two anchor frames, a picture to be displayed, and the incoming compressed bitstream. + This research is partly sponsored by Medianix Semiconductor, Inc. Contributed Paper Manuscript received April 13, 1998 0098 3063/98 $10.00 1998 IEEE