Design of Low Power and High Speed Comparator with sub-32-nm Double Gate-MOSFET V.R.Bhumireddy * , K.A.Shaik † , A.Amara † , S.Sen ‡ , C.D.Parikh § , D.Nagchoudhuri ‡ , A.Ioinovici ¶ * NXP Semiconductors, INDIA, Bangalore- venkata.ratnam@nxp.com † Institut Suprieur d’Electronique de Paris(ISEP), FRANCE, Paris -{kshaik, amara.amara}@isep.fr ‡ Dhirubhai Ambani-Insistute of ICT (DA-IICT), INDIA, Gandhianagar, Gujarat - {subhajit sen, dnc}@daiict.ac.in § Ahmedabad University, INDIA, Ahmedabad, Gujarat - chetan˙ parikh@ahduni.edu.in ¶ Sun Yat-sen University, CHINA, Guangzhou, Guangdong - ioinovici@hait.ac.il Abstract—A novel latch-based comparator is proposed for Successive Approximation (SA) Analog to Digital Conver- tor(ADC)with sub-32nm Double Gate MOSFETs(DG-MOSFET). The regeneration time of the latch is improved by using an extra positive feedback which uses the threshold voltage mod- ulation property of DG-MOSFET. Simulation of the proposed comparator with CEA-LETI’s DG-MOSFETmodels resulted in a delay of 25ps. The average power dissipation over one clock period is ≤ 1μW up to the clock frequency of 100MHz, which increases as frequency is increased resulting in an average power of 6.54μW at 1GHz, for an input voltage differential of 50mV. Index Terms—Comparator, DG-MOSFET, Regeneration time, Kickback noise I. I NTRODUCTION Comparator is an essential building block of Successive Approximation Analog to Digital Converter (SA-ADC) which is the most promising ADC for low power and average speed applications. The speed, power consumption and the area are the most important factors in design of comparators for SA- ADC. The ever-growing low-power demand application of portable devices makes the power consumption a very critical constraint for circuit designers. High speed and low power consumption are important features of many ADC designs to reduce energy used or to minimize heat dissipation to lower cooling and packaging costs [1]. The proposed comparator finds wide range of applications including data converters, signal processing and switching power regulators [2] [1]. Dynamic comparator is used to reduce the power consump- tion by cutting off the current path from VDD to VSS before and after decision. But still most of the power is consumed during the regeneration time. To reduce the power dissipation and increase the speed further, reducing the regeneration time is very effective. This paper presents a comparator, in which the regeneration time is reduced using the advantage of the second gate of the Double Gate- MOSFET. To reduce the signal dependent dynamic offset, a constant common mode voltage of VDD/2 is chosen for the proposed comparator inputs. Preamplifier takes more power and hence the proposed This work is financed by Indo-French Centre for the Promotion of Advanced(IFCPAR)under the project No.4100 IT-1 Fig. 1. Schematic of n type DG-MOSFET [3] comparator is designed without preamplifier. The organization of this paper is as follows, section I presents the introduction and section II includes the brief description of present Fully Depleted Silicon on Insulator Independent Gate Double Gate MOSFET (DG-MOSFET). Section III presents existing archi- tectures of latched comparators while Section IV presents the DG-MOSFET implementation of Song’s comparator [4] and the proposed comparator. Section V presented the simulation results of the proposed comparator and comparisons with the comparators in the literature. Finally section VI concludes this paper. II. FULLY DEPLETED SILICON ON INSULATOR DG-MOSFET Ultra-thin film body Silicon-On-Insulator (SOI) Double Gate MOSFET (DG-MOSFET) is one of the most promising devices, with reduced short channel effects and possible to scale down to 10 nm technology node. Advantages of SOI technology over bulk silicon include: 1) high speed and low leakage currents 2) total dielectric isolation between devices which aid to improve noise immunity 3) higher saturation currents with reduced floating body effects [5]. The advantages of SOI DG-MOSFET are: 1) a good electrostatic coupling between the conduction channel and the gate electrode, 2) nearly ideal sub threshold slope (60mV/decade at room tem- perature), 3) reduced short channel effects in sub-50 nm technology and 4) low voltage circuit design [3]. All these properties of DG-MOSFET motivates to use this device in 978-1-4799-1337-4/13/$31.00 ©2013 IEEE 2013 IEEE INTERNATIONAL CONFERENCE ON CIRCUITS AND SYSTEMS 1