Comparative study of the fabricated and simulated Impact Ionization MOS (IMOS) F. Mayer * , C. Le Royer, G. Le Carval, C. Tabone, L. Clavelier, S. Deleonibus CEA-DRT-LETI-CEA/GRE – 17, rue des Martyrs, 38 054 Grenoble Cedex 9, France The review of this paper was arranged by Simon Deleonibus Abstract Drift diffusion phenomena limits the subthreshold slope of conventional MOSFET to 60 mV/dec at room temperature. This paper deals with a new type of device, the Impact Ionization MOS (IMOS), which exhibits subthreshold slopes down to a few mV/dec. The electrical results of the fabricated IMOS are analysed and the scalability of this device is investigated thanks to TCAD simulations. The scaling of the dimensions allows a drastic reduction of the supply voltage and higher ON currents, but nanometer-large IMOS exhi- bit higher OFF current too due to Band-to-Band Tunnelling. Ó 2007 Elsevier Ltd. All rights reserved. Keywords: Impact ionization; I-MOS; Subthreshold slope; Threshold voltage 1. Introduction The concept of the Impact Ionization MOS (IMOS) was first proposed in 2002 by Gopalakrishnan et al. [1]. Its design is far different from the classical MOSFET’s one. The IMOS is based on a PiN structure, with a gate which does not cover entirely the intrinsic area. Whereas the sub- threshold slope of the MOSFET is limited to 60 mV/dec at room temperature by the drift diffusion phenomena, the IMOS uses impact ionization to provide carriers, which allows subthreshold slopes as low as 5 mV/dec. With such a slope, the threshold voltage can be reduced and the I ON / I OFF trade off can be simultaneously improved. A band diagram of a p-IMOS is plotted in Fig. 1, explaining the operation mode of the device. The feasibility of this device has already been demonstrated by Gopalakrishnan et al. [2] and Choi et al. [3]. The purpose of this paper is a deeper study compared to [4] in order to investigate the impact of the drain/source polarization (V ds ) on the threshold volt- age and on the subthreshold slope of the fabricated devices and to compare these results with TCAD simulations of smaller devices to gain an insight into the scalability of the IMOS. 2. Device fabrication Fig. 2 shows a full CMOS compatible process flow used for the IMOS. The devices were fabricated on Silicon On Insulator (SOI) wafers (100 nm Si film layer). The isolation is ensured by MESA structures. Choi et al. have shown that the use of a buried oxide reduces the leakage current and improves the overall performances of the IMOS [5]. Firstly, a SiO 2 /poly silicon gate stack is formed (oxide thickness: 9 nm) followed by a 10 nm L-shaped nitride spacer. Then source and drain are raised (30 nm) by selec- tive epitaxy of silicon. Thanks to two level masks, source and drain are doped asymmetrically (BF 2 and As). The space between the N implantation level and the gate edge forms, in the case of the p-IMOS, the intrinsic area 0038-1101/$ - see front matter Ó 2007 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2007.02.015 * Corresponding author. E-mail address: frederic.mayer@cea.fr (F. Mayer). www.elsevier.com/locate/sse Solid-State Electronics 51 (2007) 579–584