IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 63, NO. 11, NOVEMBER 2016 4409 Reliability Degradation Mechanisms of Horizontal Current Bipolar Transistor Josip Žilak, Student Member, IEEE, Marko Koriˇ ci´ c, Member, IEEE, and Tomislav Suligoj, Member, IEEE Abstract—The impact of the reverse-bias emitter-base stress and the mixed-mode stress on horizontal current bipolar tran- sistor (HCBT) reliability characteristics is analyzed. Under the stress conditions, hot carriers are generated and injected toward silicon-oxide interfaces above and below HCBT’s emit- ter n + polysilicon region where the traps responsible for the base current and beta (β) degradations are formed. Different degradation rates of three HCBT structures measured under both stresses suggest various contributions of the top and bottom oxides to total damage. A larger contribution of the top interface under the reverse-bias emitter-base stress and of the bottom interface under the mixed-mode stress is determined. A lower doping concentration in the bottom part of the intrinsic transistor and a shorter emitter polysilicon predeposition oxide etching both reduce the generation of interface traps during stress tests. The time-dependent trap degradation simulations are run on the structures with the realistic doping profiles to explain the measured stress data on various HCBT structures. Index Terms— Horizontal current bipolar transistor (HCBT), mixed-mode stress, reliability, reverse-bias emitter-base (EB) stress, silicon-oxide interface. I. I NTRODUCTION T HE downscaling of bipolar devices and a constant quest for higher speeds result in lower breakdown voltages and increased operating current densities that tighten the safe- operating-area (SOA) of transistors. In addition, an increased electric field due to lateral and vertical scaling makes the robust and reliable Si and SiGe bipolar device development more challenging, increasing the importance of reliability examinations [1], [2]. The device reliability testing in standard operating conditions would be very long (e.g., >10 years), so accelerated stress methods, such as a reverse-bias emitter- base (EB) stress, a high forward current, and, lately, a mixed- mode stress, are typically used in the reliability estimation. Stress conditions accelerate the damage mechanisms providing the stress data in shorter time that can be used in determination of the SOA, prediction of the device electrical characteristics degradation, and extraction of the device lifetime as shown in [3] and [4]. The high electric field, produced within devices Manuscript received July 1, 2016; revised September 1, 2016; accepted September 14, 2016. Date of publication October 4, 2016; date of current version October 20, 2016. This work was supported by the Croatian Science Foundation through the HIPERSEMI Project under Contract 9006. The review of this paper was arranged by Editor E. Rosenbaum. The authors are with the Micro- and Nano-electronics Laboratory, Depart- ment of Electronics, Faculty of Electrical Engineering and Computing, University of Zagreb, 10000 Zagreb, Croatia (e-mail: josip.zilak@fer.hr; marko.koricic@fer.hr; tomislav.suligoj@fer.hr). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2016.2611246 under the stress conditions, increases the impact ionization and hot carrier generation. Movement of the hot carriers toward the silicon-oxide interface and possible trap generation under their interaction with passivated dangling bonds at the interface make the reliability damage physics rather compli- cated [1]. The generated traps act as generation–recombination (G-R) centers causing a base current ( I B ) increase, which is more pronounced at lower base-emitter voltage (V BE ), and consequently degradation of a dc current gain (β ) and a device lifetime [3]–[8]. Furthermore, the impact of these excess G-R centers on a 1/ f noise has been investigated. It was shown that 1/ f noise performance is degraded, which affects the spectral purity of nonlinear RF circuits (e.g., VCO) [8]–[10]. DC stress measurements have been reported to degrade the small-signal parameters of a SiGe HBT, but the amount of the degradation is heavily dependent on the device design and process technology [5], [8]. Moreover, high-power RF signals also generate the hot carriers, and are used for reliability testing in circuit environment. This RF stress also increases I B , which can cause increased power consumption in circuits, but there is no significant degradation to linearity and power gain of LNAs and PAs, as studied in [4], [5], and [11]–[13]. Physics-based TCAD modeling of all stress degradation mechanisms based on the time-dependent stress data com- bined with device-to-circuit reliability interaction is paving the way toward the compact models, which will eventually make it possible to predict the time-to-failure of complex circuits [5], [14], [15]. The horizontal current bipolar transistor (HCBT) is a lateral bipolar transistor with the active region processed in the silicon sidewall defined by the shallow trench isolation. Due to its compact structure, HCBT is integrated with CMOS with only two or three additional lithography masks and a small number of additional process steps, resulting in a low-cost BiCMOS technology platform suitable for wireless communication cir- cuits [16]. HCBT is fabricated with optimized doping profiles, which results in the state-of-the-art high-frequency characteris- tics among the implanted-base silicon bipolar transistors. The cut-off frequency f T = 51 GHz, the maximum frequency of oscillations f max = 61 GHz, and the common-emitter break- down voltage BV CEO = 3.4 V are reported, resulting in the f T BV CEO product of 173 GHzV. Furthermore, high-voltage HCBTs with the breakdown voltages up to 36 V [17] can be fabricated together with the high-speed HCBTs and CMOS, broadening the application spectrum of the technology. An initial reliability examination of HCBT structures is presented in [10]. In this paper, the stress measurements 0018-9383 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.