IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO. 10, OCTOBER 2001 961 Design and Implementation of a Low-Voltage Fast-Switching Mixed-Signal-Controlled Frequency Synthesizer Tzi-Dar Chiueh, Jin-Bin Yang, and Jen-Shi Wu Abstract—A new frequency synthesizer based on combining the analog phase-locked loop (PLL) and the all digital PLL (ADPLL) is presented. The frequency synthesizer achieves high frequency resolution, broad frequency range, high switching speed, and low supply voltage. The oscillator is controlled by both the digital control word and the control voltage of the analog PLL. It is an array oscillator implemented by symmetric load differential inverting buffers which provide better rejection to supply noise and fabrication variance. Fractional- divider and delay inter- polation technique are employed to enhance the divider resolution without inducing jitter. A binary search algorithm is used to find the proper digital frequency control word, which can be saved for later use and greatly speed up the frequency switching process. Fabricated using a 0.6- m SPTM CMOS process, the synthesizer achieves a frequency range of 54–154 MHz with a frequency error less than 1 ppm and a frequency switching time less than 10 s. The chip consumes very little power and draws 47 mW from a 2-V supply voltage. Index Terms—Frequency synthesizer, mixed-signal control, phase-locked loop (PLL). I. INTRODUCTION W IRELESS transmission almost always suffers severe interferences from various sources. Spread spectrum techniques have been applied successfully to combat the impair- ments in all sorts of wireless channels. Specifically, frequency hopping spread spectrum (FHSS) approach has been adopted by several commercial wireless communication standards, such as IEEE 802.11 wireless LAN, Bluetooth (http://www.blue- tooth.com), and HomeRF (http://www.homerf.org). Fig. 1 shows the block diagrams of the transmitter and the receiver in a frequency hopping spread spectrum system. In a frequency hopping spread spectrum system, the available channel band- width is subdivided into frequency slots. Selection of these slots in each time interval is controlled by a PN code generator. The receiver must know and synchronize itself with this PN Manuscript received October 26, 1999; revised September 28, 2001. This paper was recommended by Associate Editor W. Serdijn. T.-D. Chiueh is with the Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan 10617, R.O.C. J.-B. Yang was with the Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan 10617, R.O.C. He is now with Mediatek, Inc., Hsinchu 300, Taiwan, R.O.C. J.-S. Wu was with the Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan 10617, R.O.C. He is now with VXIS Technology Company, Hsinchu 300, Taiwan, R.O.C. Publisher Item Identifier S 1057-7130(01)11051-7. code to correctly demodulate the incoming signal. Since the PN code generator in a FHSS system switches carrier frequency frequently (as fast as once every 1 ms), a fast-switching and stable (low-jitter) frequency synthesizer for generating the hopping carrier frequency is essential to FHSS transmitters and receivers. Conventionally, frequency synthesizers are designed using analog phase-locked loop (PLL) [1] or direct-digital synthesizer (DDS) [2]. The analog approach provides higher frequency res- olution, but suffers slow acquisition. On the contrary, the digital approach has low frequency range and poor frequency resolu- tion, but can achieve very fast switching. An analog PLL usually includes a voltage control oscillator (VCO) to generate a periodic signal synchronized to a partic- ular reference signal. The frequency of the periodic signal is controlled by an analog voltage, which is adjusted through a feedback loop. Generally, the feedback loop includes a phase frequency detector (PFD) and a loop filter. The PFD is used for generating a phase error signal which represents the phase dif- ference between the periodic signal and the reference signal. The loop filter and a charge pump circuit are used for inte- grating the phase error generated from the PFD to output a con- trol voltage. This control voltage generated from the loop filter is fed back to control the frequency of the periodic signal from the VCO. The control of this voltage over the frequency of the peri- odic signal is continuous and, therefore, the analog PLL can pro- vide a good frequency resolution. However, the loop bandwidth of the analog PLL has to be carefully designed to ensure that the oscillation signal from the PLL have a proper phase noise level and a fast settling process. In addition to the traditional analog PLLs, there is another ap- proach called all-digital (ADPLL) [3]. The ADPLL employs a digital-controlled oscillator (DCO) to replace the voltage-con- trolled oscillator (VCO) in traditional PLLs. Because a special algorithm is used to search for the digital control word in the digital controlled oscillator, the digital PLL can capture the fre- quency in only 50 clock cycles, much faster then if analog PLLs are used. Although the ADPLL is very agile, it still has some problems, namely, poor frequency resolution and nonuniform frequency step size. In this paper, a frequency synthesizer architecture that possesses both the advantages of high frequency resolution of analog PLLs and fast frequency acquisition of digital PLLs is proposed. The kernel of the synthesizer is a mixed-signal-con- trolled PLL which employs two types of control: analog and digital. With the flexibility and programmability of a 1057–7130/01$10.00 © 2001 IEEE