Vol.:(0123456789) 1 3 Applied Physics A (2020) 126:45 https://doi.org/10.1007/s00339-019-3229-x Design and performance enhancement of doping‑less feld efect transistor with the help of negative capacitance technique Lubna Gajal 1  · Naveen Kumar 2  · S. Intekhab Amin 3  · Sunny Anand 1 Received: 27 September 2019 / Accepted: 11 December 2019 © Springer-Verlag GmbH Germany, part of Springer Nature 2019 Abstract The performance exploration of doping-less negative capacitance FET (NC-FET) has been proposed for the novelty of an exceedingly low power consumption device. A ferroelectric material, PZT (lead zirconate titanate), has been used as a gate insulator to perceive the efects of negative capacitance, and thus doping-less FET is modifed into doping-less NC-FET for low power consumption. Ferroelectric materials are similar to dielectric material except for the property of polarization, and PZT gives adequate polarization rate with high dielectric capacitance and better reliability. In this pursuit, hysteresis behavior depends on the thickness of PZT (t FE ) therefore suitable tuning of ferroelectric thickness is an important design parameter to optimize the device performance to achieve lower subthreshold swing (SS < 60 mV) at lower threshold voltage for the proposed doping-less NC-FET device. In addition, the thickness of PZT is varied for further improvement where it shows higher t FE values improve the hysteretic behavior and augmented value of PZT thickness preserve the device in a non-hysteretic mode which is responsible for the absolute improvement in this proposed device. After t FE = 6.23 × 10 −5  cm, the operation of the proposed device drives the hysteretic mode. In this context, the electrical properties of the device have been inspected to demonstrate the hysteretic and non-hysteretic action. 1 Introduction Reducing the power consumption of extreme-scaled devices is a high demand for the next generation FET technology [1]. Negative capacitance feld efect transistor (NC-FET) is one of the prominent devices that use a ferroelectric (FE) material as a gate insulator to reduce the power consump- tion [2–8]. Other benefts of using ferroelectric materials are that the input gate voltage gets amplifed internally that afects the increase in the ON current, and hence, the low subthreshold slope can be achieved. Ferroelectric materials are similar to dielectric material except for the property of polarization. Ferroelectric materials are able to get polarized even when there is no electric feld applied, hence known as spontaneous electric polarization [9]. By applying an external electric feld, spontaneous electric polarization of the ferroelectric material can be altered. The spontaneous electric polarization of such materials involves an efect of hysteresis which can be used as a memory purpose. Also, there are two parameters such as peripheral stress and tem- perature that can interchange the spontaneous polarization. The formation of spontaneous polarization by the use of stress and temperature is called piezoelectricity and pyro- electricity, respectively [10, 11]. The combined properties of pyroelectricity, memory, and piezoelectricity enable the ferroelectric capacitors in the applications of sensors. The ferroelectric materials like PZT (PbZr/TiO 3 ), BaTiO 3 , PbTiO 3 etc., are widely used in FET technology. In the year 2008, Salahuddin et al. [12] frst published that sub- threshold slope can be lowered below the fundamental limit (SS < 60 mV) by using negative diferential capacitance as a gate insulator in MOSFET. Khan et al. [13] then proposed an antiferroelectric mode of negative capacitance FET in the year 2011, which shows sub-60 mV decade −1 subthreshold * S. Intekhab Amin samin@jmi.ac.in Lubna Gajal lubna.wania@gmail.com Naveen Kumar nk9727@gmail.com Sunny Anand sunnyanand.42@gmail.com 1 Amity University, Sector-125, Noida, Uttar Pradesh, India 2 Dr. B.R. Ambedkar National Institute of Technology, Jalandhar, Punjab, India 3 Jamia Milia Islamia University, New Delhi, India