The growth of carbon nanotubes on electrically conductive ZrN support layers for through-silicon vias Sten Vollebregt a, ⁎, Sourish Banerjee a, 1, Frans D. Tichelaar b , Ryoichi Ishihara a a Delft University of Technology, Else Kooi Laboratory, Faculty of Electrical Engineering, Mathematics and Computers Science, Laboratory of Electronic Components, Technology and Materials, Feldmannweg 17, 2628 CT Delft, The Netherlands b Delft University of Technology, Kavli Institute of Nanoscience, Faculty of Applied Physics, National Centre for High Resolution Electron Microscopy, Lorentzweg 1, 2628 CJ Delft, The Netherlands abstract article info Article history: Received 17 June 2015 Received in revised form 19 January 2016 Accepted 25 January 2016 Available online 29 January 2016 State-of-the-art Cu-based through-silicon vias (TSVs) suffer from filling difficulties and reliability concerns. Carbon nanotubes (CNTs) are an attractive alternative filler material for TSV due to their high aspect ratio, attractive mechanical and thermal properties and high current carrying capability. However, so far tall enough CNT could only be grown on electrically insulating layers, limiting their electrical applications. In this work we demonstrate and investigate the growth of CNT with aspect ratios up to 30 on electrically conductive ZrN layers. This was used to fabricate the first CNT TSV devices which are contacted on both sides of the bundle by metal thin-films, instead of probe needles, which were subsequently electrically characterised. © 2016 Elsevier B.V. All rights reserved. Keywords: Carbon nanotubes Chemical vapour deposition Vertical interconnects Through silicon vias 1. Introduction Three-dimensional (3D) integration has been suggested as a tech- nique to reduce the delay and power losses of interconnects in very large-scale integration by allowing shorter wires to be routed between logic cells. Furthermore, this technique can be used to integrate differ- ent semiconductor technologies into a single package, for instance com- bining sensors and their read-out electronics fabricated in two different active layers [1,2]. Through-silicon vias (TSVs) are an essential compo- nent for 3D integration using die or wafer stacking [3]. With traditional wire bonding the number of connections between two stacked dies is limited to the periphery, while TSV can be used to connect the different active layers virtually anywhere over the die. TSV technology recently led to commercial applications in, for instance, stacked memory cells for large-scale computing [4]. Current TSV technology uses electroplated Cu as metal filler in com- bination with deep reactive ion etching (DRIE) to fabricate the through- silicon holes. In a conventional CMOS process the TSVs are fabricated after the logic circuits. This means that, in order to reach the back-side of the wafer or die, the holes have to be etched through the layer con- taining the active devices. Due to the limited aspect ratio (AR) of DRIE, and especially to ensure void-free Cu electroplating, much of the device area is lost to reserve space for these Cu TSV. This issue is partly resolved by wafer thinning to allow for smaller vias, however, this results in frag- ile wafers which complicate handling. Another issue with Cu as filler metal is the mismatch in the thermal expansion coefficient with Si which gives rise to stress. This introduces additional failure mechanisms in the back-end metal stack and influences the performance of nearby transistors, thus requiring a large exclusion zone [5]. Finally, Cu is a con- taminant for the front-end and, therefore, requires effective diffusion barriers around the TSV in order to prevent contamination of the elec- tronic devices on the chip. Carbon nanotubes (CNTs) are an attractive candidate for replacing Cu for TSV. Due to their bottom-up nature in fabrication much higher as- pect ratios are envisioned [6]. Moreover, CNT bundles have been shown to have sponge-like mechanical behaviour [7], have a low thermal ex- pansion coefficient [8], current carrying capacity up to 10 9 A/cm 2 [9], and high thermal conductivity up to 3500 W/mK [10]. Finally, according to recent models [11,12], CNT can outperform Cu in terms of electrical performance for TSV applications. High aspect ratio CNT on electrically conductive substrates are also of interest for microelectromechanical systems [13] and super-capacitors [14,15]. In order to grow CNT, chemical vapour deposition is performed in combination with a nm-thin metal catalyst which breaks up into small nanoparticles upon heating. In order for this catalyst layer to successful- ly break-up into nanoparticles, and prevent diffusion into the Si, a sup- port layer is required. An issue with current CNT TSV is that as support material only Al 2 O 3 [6,16,17] or SiO 2 [18] has been used. Both are elec- trical insulators. While it has been demonstrated that it is possible to contact the CNT through b 2 nm Al 2 O 3 layers [19], this will result in a rel- atively high ohmic contact to the CNT as tunnelling will be the electrical Microelectronic Engineering 156 (2016) 126–130 ⁎ Corresponding author. E-mail address: s.vollebregt@tudelft.nl (S. Vollebregt). 1 Present address: University of Twente, Semiconductor Components group, MESA+ Institute for Nanotechnology, Hallenweg 15, 7522 NB, Enschede, The Netherlands. http://dx.doi.org/10.1016/j.mee.2016.01.034 0167-9317/© 2016 Elsevier B.V. All rights reserved. Contents lists available at ScienceDirect Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee