Analysis and optimization of RC delay in vertical nanoplate FET Changbeom Woo a , Kyul Ko a , Jongsu Kim a , Minsoo Kim a , Myounggon Kang b , Hyungcheol Shin a,⇑ a Inter University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-744, South Korea b Department of Electronics Engineering, Korea National University of Transportation, Chungju-City 380-702, South Korea article info Article history: Available online xxxx The review of this paper was arranged by A.A. Iliadis, A. Akturk, R.P. Tompkins, and A. Zaslavsky Keywords: Vertical nanoplate FET (VNPFET) Short channel effects (SCEs) Intrinsic gate delay Improved performance abstract In this paper, we have analyzed short channel effects (SCEs) and RC delay with Vertical nanoplate FET (VNFET) using 3-D Technology computer-aided design (TCAD) simulation. The device is based on International Technology Road-map for Semiconductor (ITRS) 2013 recommendations, and it has initially gate length (L G ) of 12.2 nm, channel thickness (T ch ) of 4 nm, and spacer length (L SD ) of 6 nm. To obtain improved performance by reducing RC delay, each dimension is adjusted (L G = 12.2 nm, T ch = 6 nm, L SD = 11.9 nm). It has each characteristic in this dimension (I on /I off = 1.64  10 5 , Subthreshold swing (S.S.) = 73 mV/dec, Drain-induced barrier lowering (DIBL) = 60 mV/V, and RC delay = 0.214 ps). Furthermore, with long shallow trench isolation (STI) length and thick insulator thickness (T i ), we can reduce RC delay from 0.214 ps to 0.163 ps. It is about a 23.8% reduction. Without decreasing drain cur- rent, there is a reduction of RC delay as reducing outer fringing capacitance (C of ). Finally, when source/ drain spacer length is set to be different, we have verified RC delay to be optimum. Ó 2017 Published by Elsevier Ltd. 1. Introduction As scaling of the conventional CMOS device has reached its lim- its [1], new technology is needed for continued performance gain. Silicon nanoplate based on CMOS technology has shown promising prospects as the next generation device [2]. Nanoplate with gate- all-around (GAA) structure has better electrostatic gate controlla- bility than FinFET [3,4]. Also, compared to nanowire FET, it has higher electron density and drain current because it has large cur- rent area. Thus, it is used as channel because nanoplate is the promising structure following FinFET. The conventional device like lateral field effect transistor (LFET) is still severely limited by the gate length (L G ), the spacer length (L SD ), and source/drain contact size. To overcome these limits and improve scalability, vertical field effect transistor (VFET) was proposed by fabricating the chan- nel in vertical direction [5–8]. CMOS technology based on vertical nanoplate FET (VNPFET) has potential to achieve better intrinsic gate delay because L G and L SD can be adjusted without spatial constraints. In this work, we have focused on optimizing VNPFET by adjust- ing L G , channel thickness (T ch ), L SD , shallow trench isolation (STI) length, and insulator thickness (T i ). In addition, we have tried to obtain better intrinsic gate delay by being different source/drain spacer length through VFET with process which is not commonly used for LFET. 2. Device structure As the next generation device, we have used nanoplate struc- tured for VFET. Nanoplate has some advantages. It shows better electrostatic gate controllability than FinFET because it has GAA structure [3]. Also, compared to nanowire FET, it has better charge density and drain current due to large current path. To analyze the characteristics, it was performed by 3D TCAD simulation [9]. The structure and parameter of VNPFET device are shown in Fig. 1(a) and (b) [10]. There are source, gate, and drain in vertical direction. STI located near drain acts as cutoff from other devices [11]. Source and drain doping concentration (Arsenic) are 1  10 21 cm 3 . Chan- nel concentration is almost undoped since its doping (Boron) is 1  10 16 cm 3 [12]. In Table 1 shows parameter value of source contact length (L S,Con ), channel width (T W ), nanoplate height (H NP ), equivalent oxide thickness (EOT), T ch ,L G , and L SD . According to top-down approach method, H NP is assumed in 40 nm. And, L S,Con is fixed in 4 nm because source contact area is the same as the drain contact area. T W is also fixed in 40 nm to obtain high electron density. Other dimensions are based on ITRS 2013 recommendations [13]. Accordingly, L G is 12.2 nm and T ch is 4 nm respectively [14]. We have studied some characteristics by adjusting L G from 12.2 nm to 20 nm and T ch from 4 nm to http://dx.doi.org/10.1016/j.sse.2017.06.017 0038-1101/Ó 2017 Published by Elsevier Ltd. ⇑ Corresponding author. E-mail address: hcshin@snu.ac.kr (H. Shin). Solid-State Electronics xxx (2017) xxx–xxx Contents lists available at ScienceDirect Solid-State Electronics journal homepage: www.elsevier.com/locate/sse Please cite this article in press as: Woo C et al. Analysis and optimization of RC delay in vertical nanoplate FET. Solid State Electron (2017), http://dx.doi. org/10.1016/j.sse.2017.06.017