2910 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 11, NOVEMBER 2007 Performance Enhancement in Uniaxial Strained Silicon-on-Insulator N-MOSFETs Featuring Silicon–Carbon Source/Drain Regions Kah-Wee Ang, Student Member, IEEE, King-Jien Chui, Chih-Hang Tung, Senior Member, IEEE, Narayanan Balasubramanian, Ganesh S. Samudra, Member, IEEE, and Yee-Chia Yeo, Member, IEEE Abstract—We report the demonstration of a novel strained silicon-on-insulator N-MOSFET featuring silicon–carbon (Si 1-y C y ) source and drain (S/D) regions, tantalum nitride metal gate, and hafnium–aluminum oxide high-κ gate dielectric. Due to the lattice mismatch between Si 0.99 C 0.01 S/D stressors and Si, a lateral tensile strain is induced in the transistor channel, leading to substantial electron mobility enhancement. At a fixed OFF-state leakage of 100 nA/μm, the Si 1-y C y S/D N-MOSFET having a width of 4.7 μm achieves a drive current I Dsat enhancement of 16% over a control N-MOSFET. This I Dsat enhancement, which is primarily attributed to strain-induced mobility improvement, is found to increase with decreasing gate length L G due to an increased strain level in the transistor channel as the Si 1-y C y S/D stressors are placed in closer proximity. Slightly improved series resistance with Si 1-y C y S/D regions in a strained N-MOSFET accounted for approximately 2% I Dsat gain. In addition, a reduction of device width is found to reduce the drive current enhancement of the N-MOSFETs due to the presence of a transverse compressive strain in the transistor channel induced by the isolation regions. Index Terms—Lateral tensile strain, N-MOSFET, silicon– carbon (Si 1-y C y ). I. INTRODUCTION G EOMETRICAL scaling of the MOSFET has led to significant improvements in device performance and integrated circuit density. However, immense challenges are Manuscript received March 9, 2007; revised July 13, 2007. This work was supported by a research grant from the Nanoelectronics Research Program, Agency for Science, Technology and Research (A ∗ STAR), Singapore. The work of K.-W. Ang was supported by an A ∗ STAR Graduate Scholarship Award. The review of this paper was arranged by Editor V. R. Rao K.-W. Ang and G. S. Samudra are with the Silicon Nano Device Laboratory, Department of Electrical and Computer Engineering, National University of Singapore, Singapore 119260. K.-J. Chui was with the Silicon Nano Device Laboratory, Department of Electrical and Computer Engineering, National University of Singapore, Singapore 119260. He is now with the Advanced Device Technology De- partment, Taiwan Semiconductor Manufacturing Company, Hsinchu 300, Taiwan, R.O.C. C.-H. Tung and N. Balasubramanian are with the Institute of Microelec- tronics, Singapore 117685. Y.-C. Yeo is with the Silicon Nano Device Laboratory, Department of Electrical and Computer Engineering, National University of Singapore, Singapore 119260, and also with the Agency for Science, Technology and Research, Singapore 138668 (e-mail: yeo@ieee.org; eleyeoyc@nus.edu.sg). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2007.906941 faced in further device scaling. The gate dielectric thickness has been reduced to maintain good control of short-channel effects (SCE), but this leads to an exponentially increasing gate leakage current and power consumption. The level of tolerable gate leakage current and the availability of viable alternative gate dielectric technologies would determine the pace of further gate dielectric scaling. Increased channel dopant concentration is required to control SCE, but it leads to in- creased device variation and degraded carrier mobility. To further extend transistor performance, the carrier mobility in the transistor channel needs to be enhanced. Carrier mobility in silicon can be increased by strain-induced modification of the electronic band structure [1]. Therefore, channel strain engineering holds great promise for the continual improve- ment of transistor drive current and performance [2], [3]. For N-channel transistors, a boost in the electron mobility can be achieved by employing a biaxial tensile strained Si channel formed on a relaxed silicon–germanium (SiGe) buffer layer [6]–[9]. However, issues such as high defect density, self-heating effects, and narrow process window impede the manufacturability of integrated circuits fabricated on strained Si/SiGe substrates [6]–[9]. It is now generally accepted that process-induced or local strain engineering offers a more manufacturable scheme for the enhancement of carrier mobility in CMOS technology. One such process-induced strained Si approach employs a high-stress silicon nitride etch-stop liner (SiN ESL). For example, by engineering the intrinsic stress in the SiN ESL film such that it is tensile, a lateral tensile strain can be induced in the channel region of an N-MOSFET for electron mobility enhancement [10]–[12]. Yet, another simple approach to induce uniaxial tensile strain in N-MOSFETs involves the integration of silicon–carbon (Si 1-y C y or Si : C) material in the source and drain (S/D) regions [13], [14]. The lattice interaction between the lattice-mismatched Si 1-y C y S/D and the Si channel is exploited in this approach to give rise to lateral tensile strain in the transistor channel for electron mobility enhancement [15], [16]. In this paper, we demonstrate thin-body silicon-on-insulator (SOI) N-MOSFETs with silicon–carbon (Si 0.99 C 0.01 ) S/D stressors for carrier transport enhancement and an extensive characterization study to compare the electrical performance and short-channel behavior of strained and control devices. In addition to our previous report on SOI N-MOSFETs with Si 1-y C y S/D stressors [14], this paper reports further analysis 0018-9383/$25.00 © 2007 IEEE