This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS 1 Synthesis of Ternary Logic Circuits Using 2:1 Multiplexers Chetan Vudadha , Ajay Surya, Saurabh Agrawal, and M. B. Srinivas, Member, IEEE Abstract—Traditionally, binary decision diagram (BDD)-based algorithms are used to synthesize binary logic functions. A BDD can be transformed into circuit implementation by replacing each node in the BDD with a 2:1 multiplexer. Similarly, a ternary decision diagram can be transformed into circuit implementation using 3:1 Multiplexers. In this paper, we present a novel synthesis technique to implement ternary logic circuits using 2:1 multiplex- ers. Initially a methodology, which transforms a ternary logic function into a ternary-transformed binary decision diagram, is presented. This methodology is the basis for the synthesis algorithm that is used to synthesize various ternary functions using 2:1 multiplexers. Results for various ternary benchmark functions indicate that the proposed algorithm results in circuits that have, on an average 79%, and up to 99% fewer transistors when compared with the most recent 3:1 multiplexer-based algorithm available in the literature. Synthesized circuits have been implemented using carbon-nanotube field-effect transistors and simulated in HSPICE. Index Terms—CNFET, full adder, ternary logic, low power. I. I NTRODUCTION S YNTHESIS of digital circuits, with various parameter constraints, has been actively pursued over the past few decades. This has led to development of several synthesis tools that transform high-level hardware descriptions into logic circuits. These tools have been employed in development of circuits with large complexity e.g. application specific integrated circuits [1], general-purpose processor designs [2]. However, with the emergence of new computing para- digms (reversible computing [3], multi-valued logic (MVL) computing [4]) coupled with emerging devices (carbon- nanotube field effect transistor (CNFET) [5], Quantum-dot gate field effect transistor (qFET) [6]etc), there is a need for new synthesis algorithms and tools that take advantage of special characteristics of emerging devices and computing paradigms. One of the computing paradigms that has received con- siderable attention over the last few decades is MVL [7]. A recent survey presents various contemporary aspects related to MVL [4]. Some of the advantages of MVL include reduced Manuscript received January 2, 2018; revised April 9, 2018; accepted May 11, 2018. This paper was recommended by Associate Editor S. Vinco. (Corresponding author: Chetan Vudadha.) C. Vudadha, A. Surya, and S. Agrawal are with the Birla Institute of Technology and Science at Pilani, Hyderabad Campus, Hyderabad 500078, India (e-mail: chetan@hyderabad.bits-pilani.ac.in). M. B. Srinivas is with the School of Engineering and Technology, BML Munjal University, Gurgaon 122413, India. Digital Object Identifier 10.1109/TCSI.2018.2838258 interconnect complexity, less device count etc. This is due to the fact that more information is embedded per digit. For example, it is possible to represent a 14-digit (N-digit) binary number using only 9 (log 3 (2 N - 1)) ternary digits. Ternary logic is a special case of MVL with three significant states. There have been many CMOS-based implementations for ternary logic [8], [9]. It has been shown that the performance of CMOS-based designs is enhanced by adding Multi-Valued Logic (MVL) blocks to binary designs [10], [11]. A design for ternary memory units and sequential circuits has been pre- sented in [12]. A CMOS based ternary Wallace-tree multiplier has been implemented in [13]. Apart from the works which focus on novel designs [12]–[15], there have been many works which focus on synthesis of MVL logic circuits [16]–[18]. The CMOS implementations of MVL are mainly classified as current-mode circuits [19] and voltage-mode circuits [11]. While current-mode circuits require transistor biasing, voltage- mode require additional voltage sources to create multi- threshold transistors. Due to the problems in MOS-based devices and non-availability of appropriate devices, design of efficient MVL circuits has for long remained a concern [7]. But, the emergence of several new device technologies [5], [6], [20] has led to renewed interest in ternary and quaternary logic in particular. CNFETs have been used widely in the implementation of ternary logic circuits. CNFETs use single walled CNT as a conducting channel, which is either conducting or semicon- ducting depending on the angle of atom arrangement along the tube also called as chirality vector. The threshold voltage of CNFETs depends on the diameter of the CNT which in turn depends on the chirality vector. This dependence makes CNFET suitable for implementation of MVL circuits. While interest in design of CNFET-based logic circuits waned over recent years due to complex fabrication technology and reliability issues, recent demonstration of a CNFET-based processor/computer by Stanford researchers [21] has reignited this interest. An efficient design methodology, which eliminates the need for large resistances by employing an active load with P-type CNFETs, has been presented in [22] and [23]. Recently there have been many implementations of CNFET-based ternary arithmetic circuits (like Comparator [24], Adders [25]–[27], Multipliers [28] and ALU [29]) that focus on optimizing the design parameters. Recently, a synthesis technique for ternary logic circuits, which exploits the advantages of CNFET, has been presented in [30]. This technique combines the cube 1549-8328 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.