ScienceDirect IFAC-PapersOnLine 48-4 (2015) 374–379 Available online at www.sciencedirect.com 2405-8963 © 2015, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved. Peer review under responsibility of International Federation of Automatic Control. 10.1016/j.ifacol.2015.07.063 © 2015, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved. Abstract: The paper discusses the design process of a programmable logic controller implemented by means of FPGA device. Designed PLC is to be compliant with EN 61131-3 standard. Different aspects of instruction list and hardware architecture designing are presented, e.g. PLC structure with particular emphasis on central processing unit or memory map. Conclusions on an EN 61131-3 Standard are also shown. The developed PLC is implemented using FPGA device. This gives opportunity to develop interesting solutions. For example, using dual port RAM gives us opportunity to develop bit/word access without necessity of masking bits. Up to date FPGA devices have also disadvantage - there are no tri-state buffers inside. This is the reason for using multiplexers that control traffic on busses. IEC 61131-3-based PLC Implemented by means of FPGA M. Chmiel*, R. Czerwinski **, P. Smolarek*** *(*)(*) Institute of Electronics, Faculty of Automatic Control, Electronics and Computer Science, Silesian University of Technology, Akademicka Str. 16, 44-100 Gliwice, Poland (Tel: +48-32-237-14-95; e-mail: * mchmiel@polsl.pl, **rczerwinski@polsl.pl). Keywords: Control Systems, Central Processing Unit, Programmable Logic Devices, EN 61131-3 Standard, Programmable Logic Controllers. 1. INTRODUCTION The EN 61131 is a standard for programmable controllers (John and Tiegelkamp (2010)). It consists nine parts; however, the most important for Authors research investigations is third part (EN 61131-3). This part discusses programming languages. Two groups of languages are specified: text languages and graphic languages. The most common in the industry are graphical languages. On the other hand, the most comfortable form of language, during design of the controller and also for programmers, is Instruction List (IL). Instruction list is especially helpful for testing, commissioning and improving the control programs. Some manufacturers offer controllers that can be programmed using languages classified under standard EN 61131-3 (Siemens (2008), Boggs et al. (2003), Rockwell Automation (2012)). It seems very often that the hardware structure of the PLC is not compatible with the software standard - the manufacturer uses the translator that enables additional processing program written in standard-based language to the "native" language and then compiles it for that controller language (Cenelec (2013)). Such an approach often makes use of the PLC not optimal. As a matter of facts, the controller resources are not aligned with the standards. What was the motivation for research work presented in this paper? The answer is quite easy - to built PLC the structure and "the language" of which is compliant with provisions of EN 61131-3 standard. FPGAs give us opportunity to develop and test different solutions and built prototypes of PLCs (Milik (2006), Mocha and Kania (2012), Chmiel et al. (2001)). Presented design is based on classical software architecture - the PLC is realized as micro processing unit in which the action is based on the control program. Implementation of the PLC gives us chance to check advantages and disadvantages of the standard. Feasibility of the standard collections is also possible to check (Hrynkiewicz and Chmiel (2012a) (2012b)). Moreover, it is possible to embed function blocks like B-BAC written in standard-based language into PLC and increase effectiveness of the control program (Klopot et al. (2014)). The paper presents concept of classical implementation of the programmable logic controller by means of FPGA logic devices. Presented PLC conception is compatible with EN 61131-3 standard. "Classical software architecture" means software processor. In fact, it should be stated that presented solution is System on Chip. Presented CPU is really software processor; however it is supported by means of hardware modules - e.g. timers and counters are realized as hardware blocks and works in parallel (concurrent) with CPU (Chmiel and Hrynkiewicz (2005) (2010)). The paper concludes three different aspects: EN 61131-3 standard, elements of PLC structure and FPGAs resources. 2. PLC STRUCTURE There are many degrees of freedom when starting designing PLC. One constraint was obvious - EN 61131-3 standard - but other must be assumed. It has been assumed that instructions are unary or without any argument. Because of experimental and research character of the work, there is no need to built huge PLC. Basic assumptions include: data bus is 32-bit wide, address bus is 8-bit wide and control bus is 10-bit wide.