Microprocessors and Microsystems 65 (2019) 37–46 Contents lists available at ScienceDirect Microprocessors and Microsystems journal homepage: www.elsevier.com/locate/micpro FPGA-based implementation of bistable function blocks defined in the IEC 61131 M. Chmiel Institute of Electronics, Silesian University of Technology, Akademicka Str. 16, Gliwice, 44-100, Poland a r t i c l e i n f o Article history: Received 13 May 2017 Revised 19 November 2018 Accepted 27 November 2018 Available online 20 December 2018 Keywords: Programmable logic controllers (PLC) IEC 61131 Programming language Field programmable gate arrays (FPGA) Bistable function blocks a b s t r a c t This article discusses the possibilities of using FPGAs in order to construct fast PLCs that execute serial- cyclic program control loop. The PLCs bistable function blocks of the IEC 61131-3 standard with par- ticular emphasis on the possible FPGA implementations are presented. The FPGA hardware support is implemented in such a way that it does not interfere with the normal, serial-cyclic program execution. It enables a significant reduction in the timing of the result execution after loading new input data in the memory cells. Moreover, such an implementation of bistable function blocks allows for seamless use in any programming language. Both the IL text language and the graphical languages (LD and FBD) can freely use the advantages of such a solution. © 2018 Elsevier B.V. All rights reserved. 1. Introduction The EN 61131 is a standard for programmable logic controllers (PLCs) [13]. The most important, third part (EN 61131-3), discusses programming by means of five languages. Two of them are tex- tual languages: Instruction List (IL) and Structured Text (ST). The three others are graphical: Ladder Diagram (LD), Function Block Diagram (FBD), and Sequential Function Chart (SFC). However, SFC can hardly be called a programming language in the classical sense. It is rather a kind of semi-language, which allows “defining” the control algorithm in the form of the next steps and the transi- tions between them. The actions and transition conditions must be coded or recoded in one of the other languages. The most common in the industry are the graphical languages. On the other hand, the most comfortable form of language during the design of a con- troller, and also for programmers, is the Instruction List. An In- struction List is especially helpful for testing, commissioning, and improving the control programs. The third part of the IEC 61131 standard specifies the syntax and semantics of programming languages for programmable logic controllers. However, many deficiencies have been discovered and discussed in the literature. For example, such a discussion is pre- sented from the point of view of compiler developers [10,11]. Some manufacturers offer controllers that can be programmed using lan- guages classified under standard IEC 61131-3 [2,21,22]. It seems that very often the hardware structure of the PLC is not compati- E-mail address: mchmiel@polsl.pl ble with the software standard—the manufacturer uses a translator that enables additional processing programs written in a standard- based language to the “native” language and then compiles it for that microprocessor language (machine language) [14]. Such an ap- proach often makes the use of the PLC not optimal. As a matter of fact, the controller’s resources are not aligned with the stan- dards. For example, a general-purpose microprocessor can be used and the key operators of the IEC standard language can be im- plemented by means of C-language subroutines [7,8] or assembler subroutines. However, the best solutions can be achieved when IL is the “native” language of the microprocessor—graphical languages or high-level textual languages are translated into IL and IL is di- rectly compiled into binary code and implemented in the micro- processor’s Program Memory [12]. The best results for program realization can be achieved when a specialized microprocessor, compliant with IEC 61131-3, is devel- oped. The use of hardware description languages allows the de- sign of a central processing unit that can be directly implemented by means of programmable logic [3,20,22]. Moreover, a control program can be directly implemented in programmable logic as hardware modules, as is presented, among other places, in [18,19]. In this case, the program is transformed to a hardware descrip- tion language and then this description is synthesized. As a re- sult, a specific digital circuit is designed and implemented in pro- grammable logic (e.g., in an FPGA device). The parts of a PLC can be implemented as hardware modules. There is a serious advantage of such a solution: hardware sup- ported processing of the instructions may be performed quicker than by means of software solutions. For example, it would be bet- https://doi.org/10.1016/j.micpro.2018.11.006 0141-9331/© 2018 Elsevier B.V. All rights reserved.