The Dynamic Properties Investigation of the PLC CPU Implemented in FPGA M. Chmiel*., E. Hrynkiewicz** Institute of Electronics, Silesian University of Technology, Gliwice * (e-mail: miroslaw.chmiel@polsl.pl) ** (e-mail:ehrynkiewicz)@polsl.pl Abstract: The paper presents some program examples written and tested to show possibilities of construction of CPUs for PLCs build based on FPGA development platform. Presented unit is optimised for minimum response and throughput time. The constructions are based on bit-word structures of CPU and two types of data (condition) exchange methods: with acknowledge and without acknowledge – in both cases control data are passed through the set of flip-flops. Third unit is built to compare with these two. This unit is simple one processor unit which can execute both - binary and numerical operations. The experiments shown high performances of elaborated CPUs. Keywords: Programmable Logic Controller; Central Processing Unit; Bit-Word Structure of CPU; Scan Time; Throughput Time; Response Time; Concurrent Operation; Field Programmable Logic Array. 1. INTRODUCTION It may be noticed that processes for which PLCs are applied have most of all binary character or binary with small analogue component. Besides it, there are also controlled objects where analogue and digital parts are independent. This observation led the designer to the conclusion that it was possible to develop central processing units that are called bit-byte or bit-word units (see Aramaki et al., 1997). Such units consist of two processors - one for binary and one for analogue tasks. Particular processors in such units execute the assigned for them tasks. In this way such a unit makes possible parallel operation of a few processors. For such CPU the main problem for solution is the way of task assigning to particular processors and finding the gifted structure of CPU to the completion of such task assigning in practice as shown by Michel (1990). The other important problem inseparable from hardware is programming tools. Those tools should enable easy and efficient creation of control program. The programming toolbox should take benefits from all aspects of multiprocessor unit. Often bit-word CPU is designed and constructed with standard microprocessors while development of programmable logic devices creates the new possibilities in this area. The bit-word PLC CPU implemented on FPGA platform was presented by the authors in Chmiel et al. (2009). The ideas presented in (Chmiel and Hrynkiewicz, 2005; Chmiel et al., 2005) were used in that approach. The concurrent execution of instructions, as well as the processors synchronisation mechanism is presented in cited papers. Information between processors may be exchanged in two alternative ways: by means of flags written to the flip-flops set equipped with a acknowledge mechanism (see Chmiel and Hrynkiewicz, 2008) and by means of exchange memory, which was implemented in dual port RAM (see Chmiel et al., 2010). Fig. 1. CPU with data exchange mechanism. The programming language for the elaborated CPU is similar to the STL language for S7-300/400 (see Berger, 2001) and S7-200 (see Siemens, 2009) PLC Siemens families. For assigning the parts of control program to each processor special compiler was developed. Programmer writes a program in form of instructions sequence. Compiler checks the syntax and splits the sequence of instructions into two streams. Those streams are later compiled separately for each processor and written to the program memory of the particular processor. The paper deals with the problem of dynamic properties investigation of such CPUs. The dynamic features of programmable logic controller are described by means of such parameters as instruction execution time, scan time and throughput time. While working on the optimisation of PLC central processing unit, all listed above parameters must be taken into account (see Chmiel, 2008) 2. THE STRUCTURES OF BIT-WORD CPU PROCESSORS IMPLEMENTED IN FPGA For experimental and evaluation purposes, three structures of central processing unit have been designed, described in VHDL and finally implemented: CPU with two independently working processors, CPU with two