International Journal of Computer Applications (0975 – 8887) Volume 95– No.23, June 2014 1 High-Resolution CMOS Counter Type ADC Layout Design by using Transmission Gate Logic Lucky Prajapati 1 , Teena Raikwar 2 , Puran Gour 3 1,2,3 NRI Institute of Science Technology Bhopal (M.P) 462021, India Abstract: In this paper, we propose counter type ADC for high-speed applications. Counter type ADCs are one of the most popular ADC topology used to implement moderate resolution converter due to their reasonably fast conversion time and simplicity.. Designed ADC has 8 input channels each of which has 0 – 2.6 V signal range. The resolution of ADC the converter is 8 bits. The amount of passing through a system from input to output ADCs can be increased by using its technique This is implemention on the circuit level with pass transistor circuit. The primary focus of this work design and implementation of a pass transistor based Analog-to-Digital converter. The proposed counter type ADC is composed of a 8-bit DAC design by using transmission gate logic, a comparator logic , 8 bit digital counter and “AND” gates to pass the clock signal by considering the chip area, operation speed, and circuit complexity. Introduction: The measurement taken by analog instruments are continuous and slow. Analog-to-digital converters (ADCs) are use as a intermediate path between analog signal such asd voltage, current, power, frequency etc and the digital signals. Continuous time analog signal to be converted to a discrete time signal with the relationship of continuous time and descrete as t=nT, where T is the sampling time depends on sampling frequency. The digital system may consist of resistor, capacitors, transistors, linear ICs, If an analog readout is desire then it can be done by digital to analog converter ( DAC). DAC and ADC form two very important aspects of digital data processing.[3]-[4] Most physical variables are analog in natureand can take on any value within a continuous range of values. Digital system performs all their operation using digital circuitry. Thus the analog signals are converted into digital form by using analog to digital converters. Thus the analog outputs generated by transducers are fed to ADC for converting it to its equivalent digital form.The digital ouputs consist of number of bits that represents the value of analog input. Digital to analog converter is a straight forward process and is considerably eisear than ADC. The DAC is usually an integral part of any Analog to Digital Converter. [6] Designed ADC has 8 input channels each of which has 0 – 2.6 V signal range. The resolution of the converter is 8 bits. Of course, integral and dynamic nonlinearities of the converter are less than an LSB throughout the whole input signal range. One LSB is around 0.01V. The conversion time is specified as less than 10 μs with 1GHz system clock frequency. ADC Static Performance Metrics Resolution of DAC is define as the smallest change that can occur in the analog output as a result of change in the digital input. Resolution is also refer to as step size, since it is the amount that output voltage will change as the digital input value is change from one step to the next. Percentage resolution is given by[1] % Resulution = Percentage resolution is also define as the reciprocal of total number of states. This means that increase in number of bits w2ill increases the total number of steps creating smaller step size and finer resolution. The quantization step is the same as the voltage range of Least Significant Bit (LSB). Then the function DNL and INL can be defined as Where Vin (D i ) and Vin (D i-1 ) represent the input voltage corresponding the output code D i and D i-1 .[1] Differential Non-Linearity (DNL) When the step size of an ADC's output is not equal to the ideal step size, the ADC is said to have Differential nonlinearity. The DNL is a measured of the separation between one code to nearest code If the DNL is greater than 1 LSB, a non- monotonic transfer function will cause missing codes. Integral Non-Linearity (INL) Integral nonlinearity is the difference between maximum the quality of being determine digital code resolution characteristicmeasured vertically. The INL can be express as a positive INL and negative INL. The maximum difference between the actual and ideal transfer characteristic is the INL. Monotonocity: Monotonocity in a DAC that define as a digital code to the converter increases over its full scale range, the analog output never exhibit a decrease between one conversion digital voltage and the another digital voltage. In other words level or sideways position between the two end of the transfer characteristic is never negative in a monotonic- converter. Offset Errors: It is a costant differenc between the actual finite resolution characteristic and the ideal finite resolution characteristic.[1]-[4] Blocks of ADC: The our The proposed counter type ADC in the is composed of a 8-bit voltage scaling DAC, a comparator logic , 8 bit digital counter and and logic to pass the clock signal by considering the chip area, operation speed, and circuit complexity. Voltage scaling DAC convert the reference voltage Vref to a set of 2 n voltages that are decoded to a single analog output by the input digital word.The block diagram of this DAC and its layout design is shown in fig and fig