The effect of threshold voltages on the soft error rate V. Degalahal, R. Ramanarayanan, N. Vijaykrishnan, Y. Xie and M. J. Irwin Embedded and Mobile Computing Design Center Pennsylvania State University {degalaha, ramanara, vijay, yuanxie,mji}@cse.psu.edu Abstract Due to technology scaling, smaller devices and lower operating voltages, next generation circuits are highly sus- ceptible to soft errors. Another important problem con- fronting silicon scaling is static power consumption. In this paper, we analyze the effect of increasing threshold voltage (widely used for reducing static power consumption) on the soft error rate (SER). We find that increasing threshold volt- age improves SER of transmission gate based flip-flops, but can adversely affect the robustness of combinational logic due to the effect of higher threshold voltages on the atten- uation of transient pulses. We also show that clever use of high V t can improve the robustness of 6T-SRAMs. 1 Introduction Soft error phenomenon in DRAMs was known to exist as early as 1970s [16], also radiation effects on spacecraft and airplane electronics have been known for long [13]. But drastic shrinking in device sizes, associated with re- duction in operating voltages and increase in operating fre- quency, is making caches and sequential logic increasingly susceptible to soft errors from natural ground level radia- tion [12, 20, 21]. Soft errors are the most benign form of radiation effects on the circuitry, where radiation directly or indirectly induces a localized ionization capable of up- setting internal data states. While these errors result in an upset event, the circuit itself is not damaged. These er- rors are particularly troublesome for memory elements as the stored values of the bits are changed. But due to in- creasing pipeline depths in new generation processors, soft error threat to sequential circuit is very real [21, 4, 14]. In sequential logic the transient pulse usually gets attenuated. However due to the high operating frequency the probabil- ity of these errors getting latched on is increasing [6]. On another front, leakage power dissipation is challenging the rate of scaling of the CMOS technology [7]. There is a considerable industry and academic effort spent on this problem. There have been numerous techniques proposed at circuit, microarchitecture and compiler level. Leakage cur- rent is a combination of subthreshold and gate oxide leakage [22]. Subthreshold leakage can be controlled by reducing the supply voltage or by increasing the threshold voltage (V t ) of the device. Gate leakage is a less understood term, but it is known that it can be controlled by using thicker gate oxides or high K dielectrics. Also both of these depend on the gate width and gate count. Conventional ways of reducing the soft error rates include adding redundancy, increasing nodal capacitance and using error correcting codes. In this work we analyze the effect of increasing the V t of the device on soft errors in stan- dard memory elements like SRAM and flip-flop and also on combinational circuits like chain of inverters, nand gates and transmission gate based full adders, which represent the most common CMOS logic styles. We believe such an anal- ysis is very important because it helps us make intelligent design choices that reduce leakage power consumption and improve the reliability of the next generation circuits. The paper is organized as follows: Section II presents the background for soft errors, correcting schemes and related work, section III presents the theoretical premise of our scheme, section IV presents the experimental setup, section V discusses the results, and section VI presents the conclu- sions. 2 Background and related work 2.1 Soft Errors When energy particles hit the silicon substrate the kinetic energy of the particle generates electron hole pairs as they pass through p-n junctions. Some of the deposited charge will recombine to form a very short duration current pulse which causes soft error. In memory elements, these can cause bit flips, but in combinational circuits these cause temporary change in the output. In combinational logic such a pulse is naturally attenuated, but if a transient pulse is latched, it corrupts the logic state of the circuit [6, 8]. There are three principle sources of soft errors: alpha parti- cles, high-energy cosmic ray induced neutrons and neutron induced 10 B fission. Alpha particles are emitted from the packaging materials and the interaction of cosmic ray ther- mal neutron with boron present in the P-type regions of the devices [3]. A single alpha particle can generate anywhere from 4 to 16fC/m over its entire range. High-energy cosmic ray induced neutron flux is strongly de- pendent on altitude, with intensity of the cosmic ray neutron flux increasing with increasing altitude. The primary reac- tion by which cosmic ray induced neutrons cause SER is by silicon recoil. The impinging neutrons knock off the sili- con from its lattice. The displaced silicon nucleus breaks down into smaller fragments each of which generates some charge. The charge density for silicon recoils is about 25 to 150fC/m, which is more than that from alpha particle strike. So it has a higher potential to upset the circuit.