2210 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 52, NO. 6, DECEMBER 2005 Radiation-Induced Breakdown in 1.7 nm Oxynitrided Gate Oxides S. Gerardin, Student Member, IEEE, A. Cester, Member, IEEE, A. Paccagnella, Member, IEEE, G. Gasiot, P. Mazoyer, and P. Roche Abstract—We present new experimental data about the radia- tion-induced breakdown in 1.7 nm gate oxides, typical of the 90nm technology node. We irradiated several MOS capacitors with n- and p-type substrates and different areas under a positive and negative staircase bias with Ag ions. A modified testing procedure was introduced based on a low voltage sensing of the gate current during irradiation. We showed that, even in spite of a smaller gate oxide field, irradiation was more damaging for biases in deep depletion than for biases in accumulation. We attributed this to the injection in the oxide of energetic carriers heated in the depletion region. In this regime of operation, we highlighted the differences in the gate current degradation of nMOS and pMOS devices: abrupt changes followed by a smooth growth in the first ones, an increase proportional to the area in the second. Index Terms—CMOS, SEGR, ultra-thin gate oxides. I. INTRODUCTION S INCE its first observations [1]–[5], the catastrophic break- down of the MOS gate oxide produced by a single ion hit Single Event Gate Rupture (SEGR) has been the subject of several studies, focused especially on the thick oxides used in power devices, where high voltages and high electric fields are present [3], [4], [6]–[9]. SEGR was found to be characterized by a critical breakdown field: below this critical value, SEGR occurrence is not possible or, at least, extremely unlikely. The physical mechanism behind this phenomenon has not yet been fully understood [10], despite many efforts and some modeling success, mainly in the case of thick oxides. The increase in electric field due to the slower reduction of op- erating voltages compared to feature size has raised some con- cern about the occurrence of SEGR in modern deep-submicron CMOS technologies obeying Moore’s law scaling trends. Over the years, some studies have followed the scaling of the gate oxide thickness in the CMOS technology. In the last years of the past decade, three works addressed some of the basic issues of SEGR in thin sub-10 nm oxides, including testing procedures and measurement protocols, the first observation of a soft break- down in parallel to a hard breakdown reported so far, and its an- gular dependence [11]–[13]. Even more important, those works Manuscript received July 8, 2005; revised August 26, 2005. This work was supported in part by MIUR-Italy PRIN and FIRB projects. S. Gerardin, A. Cester, and A. Paccagnella are with the Dipartimento di Ingegneria dell’Informazione, Università di Padova, 35131 Padova, Italy and also with the Istituto Nazionale di Fisica Nucleare (INFN), 35131 Padova, Italy (e-mail: simone.gerardin@dei.unipd.it; andrea.cester@dei.unipd.it; alessandro.paccagnella@dei.unipd.it). G. Gasiot, P. Mazoyer, and P. Roche are with STMicroelectronics–Central R&D, 38926 Crolles Cedex, France (e-mail: gilles.gasiot@st.com; pascale.ma- zoyer@st.com; philippe.roche@st.com). Digital Object Identifier 10.1109/TNS.2005.860690 reported on the increase in the critical breakdown field for de- creasing oxide thickness, which should lie well above the max- imum electric field predicted by the technology roadmap. Those data were confirmed in a recent paper by Massengill et al. [14] which explored SEGR phenomena down to 2.2-nm oxides, and supplied the first evidence of SEGR occurrence in alternative high-K gate dielectrics. Before this work, those oxides were the thinnest submitted to SEGR testing. Despite the good amount of data collected and interpreted, some nonmarginal questions have not yet been explored in ultra- thin, sub-4 nm oxides typical of the 0.18 m and subsequent CMOS technology nodes. Among them, the effect of the gate bias polarity during irradiation on SEGR has not been clarified, since the last results [14] on MOS capacitors with ultra-thin oxides included only bias in accumulation, whereas inversion is commonly found in circuits as well. Furthermore, progres- sive breakdown [15] in ultra-thin oxides has replaced soft and hard breakdown as the characteristic failure mode, but this as- pect has not yet been investigated in SEGR studies. Finally, pMOSFET devices have never been considered in SEGR studies of ultra-thin gate dielectric. The purpose of this work is to shed some light on some of these often-neglected aspects. To this aim we have examined 1.7-nm oxinitrided gate dielectrics, typical of the 90-nm CMOS technological node, thus reducing the minimum thickness of the oxides submitted to SEGR studies. Even though we will not provide experimental data on MOS devices in strong inversion, due to the structure of the capacitors used in this work, we will show the strong impact of the depletion region on the outcome of the irradiation. Furthermore, we will highlight the differences in the degradation pattern between nMOS and pMOS devices. From a theoretical viewpoint, we will present some considera- tions about the correct evaluation of the gate oxide electric field in sub-2 nm oxides. We will also show a slightly modified SEGR testing procedure, which allows for an enhanced sensitivity on the onset of breakdown events, similar to that successfully em- ployed by our research group for devices submitted only to elec- trical stresses [16]. II. EXPERIMENTAL AND DEVICES The devices used in this study were square capacitors fab- ricated on n- and p-type substrates by STMicroelectronics, Crolles, France. The gate material was p-poly and n-poly, respectively. The gate dielectric was an oxynitrided layer, with electrical oxide thickness (EOT) 1.7 nm. Devices with different gate area were made shorting together different numbers of in- dividual 100 m 100 m capacitors. The connection between 0018-9499/$20.00 © 2005 IEEE