CIRPART – A FPGA BASED PROCESSOR FOR CIRCUIT MULTI-WAY PARTITIONING USING HYBRID GENETIC ALGORITHM S. Rajaram, Dhinesh Joseph Sukumar, S.V. Karthick, V. Abhai Kumar Department of Electronics and Communication, Thiagarajar College of Engineering, Madurai – 625015. sdhineshjoseph_conf@rediffmail.com ABSTRACT This paper proposes ‘CIRPART’ – architecture for implementing Hybrid Genetic Algorithm (GA) used for circuit Multiway Partitioning in VLSI physical design automation. CIRPART applies Hybrid Genetic Algorithm to considerably reduce the number of generations required. CIRPART provides flexibility and also achieves speedups over software based GA. CIRPART achieves more than 100x improvement in processing speed as compared to the software implementation. 1. INTRODUCTION GAs are applied to Circuit Partitioning problems since GA is more global (i.e.,) search is done from a population and not a single point and also large number of points are handled in parallel [1]. The circuit-partitioning problem [2] can be formally represented in graph theoretic notation as a weighted graph, G = (V, E) with the components represented as nodes, v i Є V where V is the vertex set and the wires connecting them as edges, e ij = (v i ,v j ) Є E where E is the edge-set. Let a i be the weight (area) of a vertex i, and c ij be the weight or cost of an edge e ij . Also given is the number of partitions k, and the capacity of each subset or partition, A 1 , A 2 ,…,A k . The output consists of disjoint subsets V 1 , V 2 ,…,V k such that U k n=1 V n = V, Vn, Σ υ i ЄVn a i <A n , and e ij such that [υ i ] ≠ [υ j ], C = Σc ij is minimized. V n = [υ i ] represents the subset containing υ i , and C is the cost of the cut. The set of edges cut by the partition, e ij , [υ i ] = [υ j ] is called the cut set. Using Sterling’s approximation [3], N k = O((n/p) (n-n/p) ). 2. PREVIOUS WORK Numerous optimization techniques have been applied to solve the graph and circuit partitioning problems [4,5,6,7,8,9]. GAs, which exhibit intrinsic parallelism provide even better solutions. Hybrid GAs [10] still speeds up the process. The use of reconfigurable hardware for the design of GA was seen in projects such as [11, 12, 13, 14, 15, 16, 17]. In the current work, all the research done in hardware implementation of GA is combined to create a system, which attempts to achieve significant speedup over software GA due to pipelining and parallelization. It also attempts to minimize the logic resources used within FPGA. It applies Hybrid Genetic Algorithm to perform local optimization in every generation. This results in faster convergence and hence the number of generations is considerably reduced. 3. NEED FOR HARDWARE REALIZATION OF GENETIC ALGORITHM Reconfigurability is essential in a general- purpose GA engine because certain GA modules require changeability). Thus a hardware-based GA is both feasible and desirable. Work by Spears and De Jong [18] indicates that for NP-complete problems, m=100 and g=100 may be necessary to obtain a good result and avoid premature convergence to a local optimum. Because a general-purpose GA engine requires certain parts of its design to