International Journal of High Speed Electronics and Systems Vol. XX, No. X (2010) 1–7 World Scientific Publishing Company 1 COMPOUND SEMICONDUCTOR BASED TUNNEL TRANSISTOR LOGIC SUMAN DATTA Department of Electrical Engineering, The Pennsylvania State University, University Park, PA 16802, USA * sdatta@engr.psu.edu Received (Day Month Year) Revised (Day Month Year) Accepted (Day Month Year) We introduce a new transistor architecture based on inter-band tunneling mechanism as a step towards exploring steep switching transistors for energy efficient logic applications. While there have been reports on tunnel transistors in Si, Ge material system and their alloys, we focus specifically on narrow gap compound semiconductor (CS) systems to develop tunnel transistors. We address the following topics regarding the CS-based tunnel transistor architecture: a) the choice of appropriate materials to tune the transfer characteristics over a specified gate voltage swing b) the characteristic screening lengths in these device essential for scaling, c) an effective way to estimate the switching speed of tunnel transistors, d) digital circuit design methodologies utilizing tunnel transistors. Keywords: Tunnel FET; InGaAs; logic; SRAM 1. Introduction Continued miniaturization of the silicon CMOS transistor technology, has resulted in an unprecedented increase in single-core and multi-core performance of modern-day microprocessors. However, the exponentially rising transistor count has also increased the overall power consumption, making performance per watt of energy consumption the key figure-of-merit for today’s high-performance microprocessors. Today, energy efficiency serves as the central tenet of high performance microprocessor technology at the system architecture level as well as the transistor level ushering in the era of energy efficient nanoelectronics. Aggressive supply voltage scaling while maintaining the transistor performance is a direct approach towards reducing the energy consumption since it reduces the dynamic power quadratically and the leakage power linearly. To that effect, narrow gap compound semiconductor-based (e.g. indium antimonide, indium arsenide and In x Ga 1-x As) inter-band tunnel transistor (TFET) architecture could enable the next generation of logic transistors operating below 0.5 V supply voltage. In this invited paper, we present a comprehensive study of the basic TFET architecture, the optimum materials choice to improve TFET performance, the advanced TFET * State completely without abbreviations, the affiliation and mailing address, including country. Typeset in 8 pt Times Italic.