Journal of Manufacturing Processes 27 (2017) 214–220 Contents lists available at ScienceDirect Journal of Manufacturing Processes journal homepage: www.elsevier.com/locate/manpro Technical Paper Investigation on drilling blind via of epoxy compound wafer by 532 nm Nd:YVO 4 laser Vu Nguyen-Anh Le a , Yung-Jen Chen b , Hsi-Cherng Chang c , Jau-Wen Lin d,∗ a Department of Engineering Mechanics, Nha Trang University. 02 Nguyen Dinh Chieu St., Nha Trang City, Vietnam b Advanced Semiconductor Engineering, Inc. Kaohsiung, 26, Chin 3rd Rd., N.E.P.Z., Nantze, Kaohsiung 81170, Taiwan, ROC c Air Force Institute of Technology, 198 Jieshou W. Rd., Gangshan District, Kaohsiung 82047, Taiwan, ROC d Department of Mechanical Engineering, National Kaohsiung University of Applied Sciences, 415 Jiangong Rd., Sanmin District, Kaohsiung 80778, Taiwan, ROC a r t i c l e i n f o Article history: Received 23 June 2016 Received in revised form 12 October 2016 Accepted 7 May 2017 Keywords: Laser drilling Blind via Nd:YVO4 laser Wafer level package a b s t r a c t Polymeric materials designed with macromolecular structures present different levels of absorbance against different laser wavelengths. CO 2 laser is often applied during the drilling blind via of printed circuit boards (PCB) and substrates used for semiconductor packaging since it features speedy processing time, but its high thermal energy easily causes serious substrate warpage and deformation after drilling is completed. Therefore, Nd:YVO 4 laser is selected to create low thermal energy as the tool used in this study. Factors including laser head movement speed, laser beam diameter, laser shot count, laser current and laser frequency control set at three design levels versus 12 sets of experimental parameters, comprise a total of 36 data sets to be taken into consideration. With the assistance of JMP software, a cross analysis is made in order to obtain the optimal set of parameters applicable to drill blind via on epoxy compound wafers. Finally, observations are made to explore the feasibility of applying the optimal set of parameters to drilling blind via on a macromolecular-structured polymeric material. © 2017 The Society of Manufacturing Engineers. Published by Elsevier Ltd. All rights reserved. 1. Introduction In recent years, the thriving development of portable elec- tronic products has greatly facilitated the trend of designing related products featuring high density, high performance, lightness, thin- ness, shortness and smallness parameters. Packaging with a variety of three-dimensional structures has been newly developed and designed so as to meet the needs of items becoming lighter, thinner, shorter, smaller and higher density [1–4]. Wafer level packaging (WLP), which can significantly lower the cost, has gradually gained the attention of related manufacturers. In addition to through sil- icon via (TSV) that is often used today, the three-dimensional packaging structure of vertically-stacked resin through molding via (TMV) is one of the recent developments in WLP. The pack- age structure of resin TMV is designed to place an individual chip on a chip substrate and then fill the clearance around the chip with epoxy molding compound (EMC). After the macromolecular structured polymeric material filling the clearance around the chip forms the EMC, the redistribution layer (RDL) is used to fan out the ∗ Corresponding author. E-mail address: daniel@kuas.edu.tw (J.-W. Lin). contact points of the buried chip so that the distance between con- tact points can meet the requirements of the substrate packaging for wire connection [5]. Researchers have applied the novel stacked system in package interconnect technique using a modern molding process for multi- chip which embeds in package stacking in the blending of huge zones and the minimal cost redistribution technology received from printed circuit board manufacturing [6–8]. Briindel et al. [9] have successfully investigated how to package acceleration sensors and pressure sensors using a substrateless packaging technology for wafer level fan-out. Package-on-package (PoP) embedded WLP using TMV technol- ogy has received much attention and consequent applied research. For example, PoP application was developed with an embedded WLP with Cu TMV interconnects [10]. The double-sided redistri- bution layer process including the wafer front and backside for embedded WLP to enable PoP was investigated. Yoshida et al. [11] created an ultra-thin PoP approximately 1 mm comprised of either top and bottom packages using TMV technology. Dreiza et al. [12] studied the application for next generation high-density PoP with TMV bottom package technology. An embedded WLP PoP package of 12 mm × 12 mm × 0.8 mm with 432 I/Os using TMV was uti- lized by Chong et al. [13]. The effect of thermal performance of http://dx.doi.org/10.1016/j.jmapro.2017.05.005 1526-6125/© 2017 The Society of Manufacturing Engineers. Published by Elsevier Ltd. All rights reserved.