Ultra-Low Power Circuit Design using Double-Gate FinFETs. Abstract— In this paper, the design and performance of basic Digital (AND, OR, NAND, NOR, XOR, XNOR, NOT, Half- Adder) and Analog (Current Mirror, Cascode Current Mirror, Comparator) circuits using 20nm FinFET technology has presented. 20nm FinFET technology has been used for improvement in performance and for optimizing power mainly in Analog circuits. In this work, for different widths of NMOS and PMOS and low voltages, better results of power performance is observed in both digital and analog circuits using FinFET technology. Keywords-FinFETs, Analog Circuits, Digital Circuits, SPICE, ultra-low power. I. INTRODUCTION The steady miniaturization of the metal-oxide- semiconductor field-effect transistors (MOSFETs) with each new generation of CMOS technology has provided us with improved circuit performance and cost per function over several decades. However, three obstacles, (a) subthreshold leakage current, (b) gate-dielectric leakage, and (c) threshold voltage (Vth), have become the dominant barrier for further CMOS scaling [1]. Along with these problems, there is also an increasing class of applications, like portable electronics, microsensors, radio frequency identification, laptops, cell phones, and cameras, that demand very low power consumption and prolonged battery life. All of these applications motivated the designers to come up with several power reduction methods such as voltage scaling, switching activity reduction, architectural techniques of pipelining, device sizing, and interconnect. Out of all these methods, one that is successful is supply voltage scaling, which significantly reduces both active and static components of power. An extreme case in supply voltage scaling is subthreshold circuit design. It has been proved that by operating in the subthreshold region, circuits consume minimum energy per operation [2]-[5]. FinFETs (fin-type field effect transistors) [6], offer interesting power-delay tradeoffs and better characteristics (short-channel-effects) in the nanometer regime in order to meet the performance expected by the ITRS for the forthcoming technological nodes [7]. Furthermore, bulk architecture requires a high channel doping density in order to control the short channel effects, leading to large transversal electric fields and unacceptable degradation of the electron mobility. Double-gate (DG) FinFETs are broadly classified into two types, namely, simultaneously driven double-gate (SDDG) and independently driven double gate (IDDG) [8], [9] FinFETs. Due to nonplanar structure, and the width quantization effect of FinFET devices still suffers from the issue such as process complexity and additional parasitic capacitance; however it is promising candidate for the nanometer regime. Particularly in analog applications, the width quantization effect [10] is important and also where the self-loading dominates. For example, increasing the active width of the device increases the current and the load capacitance in the same ratio, thereby making the delay invariant. The channel width of the single fin device is restricted by the height of the fin HFIN. The channel width for a multi gate device is given by following [11]: W ~ 2HFIN + WFIN (1) Where WFIN is the fin width. For a device having HFIN = 60 nm and WFIN = 10 nm, the effective channel width can be calculated [from (1)] as 130 nm. For technologies below 20-nm channel length, such a high channel width only increases the static and dynamic power dissipation (due to the higher currents) for a given value of delay. Fig. 1.1 shows the structure of a FinFET. Figs. 1.2(a) and 1.2(b) show the structure of an SG- and IG-FinFET, respectively. This paper is organized as follows. Section-II explains the double-gate (DG) FinFET device structures. Section-III explains Designing of different Analog building blocks using FinFET (20nm) models. In Section-IV, Designing of different Digital building blocks using FinFET (20nm) models. Section-V describes the simulation results of designed basic circuits and finally Section-VI concludes the paper. Fig. 1.1. FinFET structure Fig. 1.2 (a). SG-FinFET 1.2 (b). IG-FinFET Ms. G. Devi Tejashwini 1 , Mr. I.B.K. Raju 1 , Mr. Gnaneshwara Chary 1 ¹Padmasri Dr. B.V. Raju Institute of Technology, CVD, ECE Department, Narsapur, Medak Dt., AP. 2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) 1 978-1-4799-1356-5/14/$31.00 ©2014 IEEE