Research Journal of Applied Sciences, Engineering and Technology 4(22): 4566-4571, 2012 ISSN: 2040-7467 © Maxwell Scientific Organization, 2012 Submitted: December 30, 2011 Accepted: March 10, 2012 Published: November 15, 2012 Corresponding Author: Mozhgan Shiri, Department of Computer Engineering, Arak Branch, Islamic Azad University, Arak, Iran 4566 A Novel Nanometric Fault Tolerant Reversible Subtractor Circuit 1 Mozhgan Shiri, 2 Majid Haghparast and 1 Vahid Shahbazi 1 Department of Computer Engineering, Arak Branch, Islamic Azad University, Arak, Iran 2 Department of Computer Engineering, Shahre-Rey Branch, Islamic Azad University, Tehran, Iran Abstract: Reversibility plays an important role when energy efficient computations are considered. Reversible logic circuits have received significant attention in quantum computing, low power CMOS design, optical information processing and nanotechnology in the recent years. This study proposes a new fault tolerant reversible half-subtractor and a new fault tolerant reversible full-subtractor circuit with nanometric scales. Also in this paper we demonstrate how the well-known and important, PERES gate and TR gate can be synthesized from parity preserving reversible gates. All the designs have nanometric scales. Keywords: Fault tolerant, nanometric circuits, nanotechnology, quantum computing, reversible logic, subtractor INTRODUCTION Reversible circuits are composed of reversible gates. In this circuits information don’t be lost. Reversible circuits can produce unique output from each input and vice versa, hence, there is a one-to-one correspondence between input and output vectors (Thapliyal and Srinivas, 2006). So a reversible logic gate has an equal number of inputs and outputs (k ×k) (Babu and Chowdhury, 2005). In ideal conditions, a reversible circuit has zero internal power dissipation because, it does not lose information. Under R. Landauer’s research in the early 1960s, the amount of energy dissipated for every irreversible bit operation is given by KTLn2 joules, where K = 1.3806505 × 10 !23 J/K is the Boltzmann’s constant and T is the absolute temperature at which operation is performed. But in 1973, Bennett showed that KTLn2 joules of energy can be saved from a system as long as the system permits the regeneration of the inputs from produced outputs (Haghparast et al., 2009; Haghparast and Navi, 2008a; Thapliyal and Gupta, 2006). A reversible gate with n-inputs and n-outputs is called a n × n reversible gate (Sastry et al., 2006). In a n × n reversible function, there are 2 n input rows and 2 n output rows in its truth table. In fact the output rows are a permutation of the input rows in the truth table (Kerntopf, 2002; Hung et al., 2006). Direct fan-outs from the reversible gate and feedbacks from a gate output directly to its inputs are not allowed (Sastry et al., 2006). Classical logic gates are called irreversible since they cannot uniquely reconstruct the input vector states from the output vector states. Synthesis and designing of a reversible gate is different from traditional logic gates (Haghparast and Sheikh, 2011). Therefore, constructing a fault tolerant reversible circuit is much more difficult than a conventional logic circuit (Parhami, 2006). In this paper, we propose a fault detection method based on parity preserving reversible logic gates. PRIMARY DEFINITIONS Some of the main measures in synthesis a reversible logic circuit are: Number of reversible logic gates, Number of garbage outputs, Number of constant inputs, Total quantum cost, and total logical calculations (Haghparast et al., 2009). Garbage outputs: One of the most important parameters in designing a reversible circuit is its garbage outputs (Hasan et al., 2004). In a reversible logic gate number of inputs and outputs is equal but all the outputs are not expected. The number of outputs added to make an n- input k-output function reversible is named garbage outputs. In fact they are needed to maintain reversibility. A heavy price is paid for every garbage output (Parhami, 2006). So, one of the major challenges in reversible logic synthesis is to minimize the garbage outputs (Hasan et al., 2004; Thapliyal et al., 2009). Quantum cost: The quantum cost of a reversible gate is the number of 2×2 reversible gates or quantum logic gates required in designing it. The quantum cost of all