IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 5, MAY 1998 547 A 160-MHz Fourth-Order Double-Sampled SC Bandpass Sigma–Delta Modulator Seyfi Bazarjani, Member, IEEE, and W. Martin Snelgrove, Member, IEEE Abstract— A fully differential double-sampled switched- capacitor (SC) architecture for a fourth-order bandpass modulator is presented. This architecture is based on a double- sampled SC delay circuit. The effect of opamp nonidealities (finite dc gain and nonzero input capacitance) on the notch frequency of this modulator is analyzed. The modulator is implemented in a 0.5- m CMOS technology and operates at a clock frequency of 80 MHz, making the effective sampling rate 160 MHz. The image signal is about 40 dB below the fundamental signal. The measured signal-to-noise-plus-distortion (SNDR) is 47 dB (not including the image) over a 1.25-MHz bandwidth centered at 40 MHz. The circuit operates at 3 V and consumes 65 mW. I. INTRODUCTION H IGH-SPEED bandpass modulators are desired in applications that require A/D conversion of narrow-band signals at IF frequencies such as digital radios and high-speed modems. Increasing the sampling frequency of a bandpass modulator allows A/D conversion of the signal at higher IF frequencies and increases the A/D resolution. In a fourth-order bandpass modulator, increasing the sampling frequency by 2 reduces the quantization noise by 15 dB adding 2.5 bits to the resolution of the A/D converter. Digitizing the analog signal at a high IF and processing the signal in the digital domain is also desirable due to the robustness of the digital circuits. Switched capacitor (SC) is the preferred analog technique for the implementation of modulators due to its high circuit accuracy. The operating speed of an SC circuit is determined by the settling time of the opamp used in the circuit. A method of increasing the sampling frequency is to use the opamp during both phases of a clock [1], i.e., double- sampling. This technique increases the sampling frequency by a factor of two without requiring a faster opamp. Double- sampling technique has already been applied to the design low-pass modulators [2], [3]. Two recently published works have utilized the double-sampled SC technique in the design of fourth-order band-pass modulators [4], [5]. A major limitation of double-sampled SC circuits is due to mismatch in the two paths [6] that causes an in-band image of the signal. However, in many digital radio systems the required Manuscript received October 10, 1997, revised February 25, 1998. This paper was supported by Nortel and by the Natural Sciences and Research Council of Canada. This paper was recommended by Guest Editors F. Maloberti and W. C. Siu. S. Bazarjani is with Qualcomm Inc., San Diego, CA 92121 USA (seyfi@qualcomm.com). W. M. Snelgrove is with the Department of Electronics, Carleton University, Ottawa, Ont. , Canada K1S 5B6. Publisher Item Identifier S 1057-7130(98)03952-4. image suppression is about 20–25 dB [7]. This requires an amplitude mismatch of less than 10% to 5.6% between the two paths. In the double-sampled SC circuit described here, path mismatch is dominated by capacitor matching. Specifically, since the first sampling capacitors determine the matching of the two paths and also dominate the total thermal noise budget , they are typically chosen to have the largest values in the modulator. In many CMOS processes capacitor mismatch typically ranges from a fraction of 1% to few percent depending on capacitor size and layout proximity. Thus, a path mismatch of less than 5.6% is easily achieved in this double-sampled bandpass sigma–delta modulator. This paper starts by introducing a -domain architecture for a fourth-order bandpass modulator. The modulator is obtained by transforming integrators to resonators in a second-order (double integration) low-pass modulator. The resulting bandpass modulator is a double-resonator modulator. In the sampled-data domain, an efficient method of implementing resonators uses two delay cells in a negative feedback loop. A double-sampled SC delay cell is presented. The impacts of nonideal circuit behaviors on the performance of a simple SC delay cell and the double-sampled SC delay circuit are analyzed. Specifically, the effect of low dc gain of the opamp on the performance of this modulator is analyzed. It is shown that a low dc gain will shift the notch frequency to a lower value and increases the in-band quantization noise. Then a SC implementation of the fourth-order bandpass modulator is presented along with Eldo [8] simulation results. Finally, the design of the modulator in a 0.5 CMOS process is considered and measured results of the modulator are presented. II. DOUBLE-SAMPLED SC BANDPASS MODULATOR In a bandpass modulator, the quantization noise is pushed away from the signal band at the desired center frequency by placing the quantization noise nulls at A simple way of designing bandpass modulators is to perform a low pass to bandpass transformation. One such transformation in the discrete-time domain is achieved by the following change of variable: (1) This transformation maps the zeros of the low-pass proto- type from dc to , suppressing the noise in the bandpass modulator around the and the frequencies. The stability and signal-to-noise ratio (SNR) characteristics of this 1057–7130/98$10.00  1998 IEEE