IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 10, OCTOBER 2004 1411 A Circuit-Compatible Model of Ballistic Carbon Nanotube Field-Effect Transistors Arijit Raychowdhury, Student Member, IEEE, Saibal Mukhopadhyay, Student Member, IEEE, and Kaushik Roy, Fellow, IEEE Abstract—Carbon nanotube field-effect transistors (CNFETs) are being extensively studied as possible successors to CMOS. Novel device structures have been fabricated and device simu- lators have been developed to estimate their performance in a sub-10-nm transistor era. This paper presents a novel method of circuit-compatible modeling of single-walled semiconducting CNFETs in their ultimate performance limit. For the first time, both the I-V and the C-V characteristics of the device have been efficiently modeled for circuit simulations. The model so devel- oped has been used to simulate arithmetic and logic blocks using HSPICE. Index Terms—Ballistic scaling, carbon nanotube (CNT), circuit- compatible model. I. INTRODUCTION A GGRESSIVE scaling of CMOS devices over different technology generations has led to higher integration den- sity and performance. However, “short channel effects” such as exponential increase in leakage current and large parameter variations stand in the way of scaling the devices much beyond 10 nm [1]. Hence, research has started in earnest to consider alternative devices and circuit architecture in a sub-10-nm tran- sistor era. Carbon nanotubes (CNTs) and molecular transistors have already gained widespread attention as possible alternative nanoscale transistors. CNTs are sheets of graphite rolled in the shape of a tube. De- pending on the direction in which the nanotubes are rolled (chi- rality), they can be either metallic or semiconducting [2]. Since their inception in the early 1990s, there has been immense re- search concerning the electrical properties of CNTs [2]–[5]. The semiconducting nanotubes have been used in high-performance transistors where the channel is the nanotube itself. High-performance carbon nanotube field-effect transistors (CNFETs) with very high “on” currents have been reported and the device physics has evolved [4], [6]. As high mobility devices are being investigated, near ballistic transport no longer seems impossible. Absence of scattering in the channel is the characteristic of ballistic devices [7]. This makes them ultrahigh speed and apt for high-performance circuit design. Manuscript received September 19, 2003; revised February 2, 2004. This work was supported in part by Semiconductor Research Corporation under Grant 1220034257, in part by the National Science Foundation under Grant EEC-0228390, and in part by the NASA-supported Institute of Nanoelectronics and Computing under Grant NCC 2-1363. This paper was recommended by Associate Editor W. Schoenmaker. The authors are with the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907-1285 USA (e-mail: araycho@ ecn.ecn.purdue.edu, sm@ecn.purdue.edu; kaushik@ecn.purdue.edu). Digital Object Identifier 10.1109/TCAD.2004.835135 Numerical device models of such ballistic CNTs have been developed. In CNFETs, the absence of dangling bonds and the possible use of aqueous dielectrics provide opportunities for high electrolytic gating [6]. This helps in achieving very high insulator capacitance, . This, in turn, improves the gate control and also lowers gate leakage. The theory of CNT transistors is still primitive and the tech- nology is still nascent [4], [8]. However, evaluation of such high-performance transistors in digital circuits is absolutely es- sential to drive the device design and understand the bottlenecks in multigigahertz processor design. However, from a circuit de- signer’s point of view, circuit simulation and evaluation using CNFETs is challenging because most of the developed models are numerical, involving self-consistent equations which circuit solvers like SPICE are not able to handle. This paper presents a novel surface potential-based SPICE compatible modeling tech- nique for single walled, semiconducting, ballistic CNTs in their ballistic limit of performance with one-dimensional (1-D) elec- trostatics. This model is applicable to a wide range of CNFETs with diameters varying from 0.6 to 3.5 nm and for all chiralities as long as they are semiconducting. This model uses suitable approximations necessary for developing any quasi-analytical, circuit-compatible compact model. Both I-V and C-V charac- teristics have been modeled. This simple model enables simula- tion of circuit transfer (dc) characteristics as well as transients. It has been validated against numerical models in [4] and [9] and has been found to be in very close agreement. It has been in- corporated in SPICE and has been used to simulate digital logic blocks, functional and processing units. The novelty of the paper lies in the fact that for the first time a simplistic model has been developed to assess circuit perfor- mance of single walled semiconducting CNFETs. It enables us to evaluate delays, estimate power in logic circuits and simulate the performance degradation due to interconnect and device par- asitics. Also, this modeling technique is generic in the sense that it can faithfully represent a wide range of CNFET geometries and gate materials with reasonable operating voltages and user specified temperature conditions. The beauty of such a model is in its strong foundation on the underlying physics of opera- tion along with necessary simplifications and assumptions. This makes a multiple-transistor circuit simulation possible. II. BALLISTIC CNFETS A. Ballistic CNFET CNTs are sheets of graphite rolled into tubes. Depending on their chirality (i.e., the direction in which the graphite sheet is 0278-0070/04$20.00 © 2004 IEEE