IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 24, NO. 3, MARCH 2005 363 Accurate Estimation of Total Leakage in Nanometer- Scale Bulk CMOS Circuits Based on Device Geometry and Doping Proﬁle Saibal Mukhopadhyay, Student Member, IEEE, Arijit Raychowdhury, Student Member, IEEE, and Kaushik Roy, Fellow, IEEE Abstract—Dramatic increase of subthreshold, gate and reverse biased junction band-to-band-tunneling (BTBT) leakage in scaled devices results in the drastic increase of total leakage power in a logic circuit. In this paper, a methodology for accurate estimation of the total leakage in a logic circuit based on the compact modeling of the different leakage current in nanoscaled bulk CMOS devices has been developed. Current models have been developed based on the device geometry, two-dimensional doping proﬁle, and oper- ating temperature. A circuit-level model of junction BTBT leakage has been developed. Simple models of the subthreshold current and the gate current have been presented. Also, the impact of quantum mechanical behavior of substrate electrons, on the circuit leakage has been analyzed. Using the compact current model, a transistor has been modeled as a sum of current sources (SCS). The SCS tran- sistor model has been used to estimate the total leakage in simple logic gates and complex logic circuits (designed with transistors of 25-nm effective length) at room and elevated temperatures. Index Terms—Band-to-band-tunneling (BTBT), doping pro- ﬁle, estimation, gate direct tunneling, halo doping, subthreshold leakage, technology scaling. I. INTRODUCTION A GGRESSIVE scaling of CMOS devices in each tech- nology generation has resulted in higher integration density and performance. Simultaneously, supply-voltage scaling has reduced the switching energy per device. However, the leakage current (i.e., the current ﬂowing through the device in its “off” state) has increased signiﬁcantly with technology scaling [1], [2]. Hence, the estimation of the total leakage is absolutely necessary for designing low-power logic circuits. Among different leakage mechanisms in scaled devices [1], three major ones can be identiﬁed as: subthreshold leakage, gate leakage, and reverse biased drain-substrate and source-substrate junction band-to-band-tunneling (BTBT) leakage [1]. With technology scaling, each of the different leakage components increases, which has two major implications in the leakage estimation and low-power logic design. First, this results in a large increase of the total leakage. Moreover, each of the Manuscript received October 9, 2003; revised April 7, 2004. This work was supported in part by the Semiconductor Research Corporation, in part by the Gigascale Silicon Research Center, in part by the Intel Corporation, and in part by the IBM Corporation. An earlier version of this paper was published in the Proceedings of the Design Automation Conference, 2003, pp. 169–174, Ana- heim, CA. This paper was recommended by Associate Editor S. Saxena. The authors are with the School of Electrical and Computer Engi- neering, Purdue University, West Lafayette, IN 47907 USA (e-mail: sm@ecn.purdue.edu; araycho@ecn.purdue.edu; kaushik@ecn.purdue.edu) Digital Object Identiﬁer 10.1109/TCAD.2004.842810 Fig. 1. Contribution of different leakage components in NMOS devices [4] at different technology generation. The leakage values are extracted using device simulation in MEDICI. values are chosen following ITRS guideline (0.7 V at 25 nm, 0.9 V at 50 nm, and 1.2 V at 90 nm). leakage components becomes equally important in nanoscaled devices. Hence, the relative magnitudes of the leakage com- ponents play a major role in low-leakage logic design. For example, it has been shown in [3] that the effectiveness of a standard leakage-reduction technique, known as “transistor stacking,” strongly depends on the contribution of the gate and the subthreshold leakage to the total leakage. Fig. 1 shows the different leakage components of NMOS devices of nm, nm, and nm taken from [4]. It can be observed that for the 90-nm device, the major leakage component is the subthreshold leakage, but in the scaled devices, contributions of the junction leakage and the gate leakage have signiﬁcantly increased. Moreover, the magnitudes of each of these components strongly depend on the device geometry (namely, channel length, oxide thickness, and transistor width), the doping proﬁles and temperature [1], [5]. Hence, an accurate estimation of leakage in nanoscaled logic circuits should be able to: 1) estimate the gate, the sub- threshold, and the junction tunneling leakage separately along with the total leakage; 2) estimate the effect of variation in doping proﬁle, transistor geometry, and temperature on indi- vidual leakage component; and 3) account for all the different physical mechanisms that can modify the leakage components to prevent both underestimation and overestimation. In this paper we have developed a methodology for estimation of the gate, the subthreshold, the junction BTBT and the total leakage of a logic circuit for different primary input vectors, based on the knowledge of: 1) the device geometry; 2) the two-dimen- sional (2-D) doping proﬁle of the device; and 3) the operating temperature. Although, a number of previous work are reported on the estimation of leakage in logic circuits [6], [7] they have 0278-0070/$20.00 © 2005 IEEE