INFLUENCE OF BARRIERS ON THE RELIABILITY OF DUAL DAMASCENE COPPER CONTACTS K.Wang¹ , ², C. J. Wilson², A. Cuthbertson¹, R. Herberholz¹, H. P. Coulson¹, A. G. O’Neill² and, A. B. Horsfall² 1 Atmel North Tyneside Ltd, Silverlink, Newcastle upon Tyne, NE28 9NZ, UK. 2 School of Electrical, Electronic and Computer Engineering, Newcastle University, NE1 7RU, UK. ABSTRACT In this paper we investigate the reliability of Cu contacts with both Ta and W based barriers using thermal and electrical stressing. The Ta based barrier showed superior resistance to electrical stressing, with a time-to-failure approaching that of the W-plug reference and a via like failure mode. However early fails reduce the t 50 due to high process induced stress imposed by the pre-metal dielectric. These initial results suggest, with further process optimization to reduce thermal stress and improve barrier uniformity, Cu contacts with Ta based barriers can be as reliable as vias in higher metals layers and the traditional W contacts. [Keywords: Copper contacts, diffusion barrier, electromigration] INTRODUCTION As ultra large scale integration dimensions shrink, the resistance of the tungsten contact becomes increasingly dominant in determining the circuit speed. By replacing this high resistance tungsten plug with a copper based contact, a higher speed of operation will be achieved. This reduction in resistance will enable the continued scaling of circuits to ever more challenging geometries. In our previous work we have demonstrated that the use of a copper contact can reduce the contact resistance by 38% [1]. In this work we discuss the implications of copper contacts on the reliability of the interconnect structure. EXPERIMENTAL A SiO 2 and BoroPhosphoSilicate Glass (BPSG) pre-metal dielectric layer (PMD) stack was used over standard 0.13μm CMOS transistors. All wafers received a standard six level Cu-metallisation process. The contact split plan used in this work is detailed in Table 1. Physical Vapor Deposition (PVD) Ta barriers were used with and without Ar+-resputter, which is intended to improve the barrier coverage at the bottom corner of the contact. An electromigration (EM) test structure comprising two M1 lines (100μm each) and one sandwich poly line (100μm); with 2 contacts was used to study electrical reliability (fig 1). A 1000 hour EM test was performed with current density of 2MA/cm 2 at 300 o C ambient. As the purpose of this work was not to characterize the lifetime of an immature barrier technology, a low 1% failure criteria was chosen to best identify the different failure mechanisms present in the barrier configurations (as discussed later). Blanket wafers with identical barrier and dielectric combinations were fabricated to study the diffusion barrier strength during thermally accelerated testing at 500 o C and 650 o C. ToF SIMS analysis was then performed to quantify any Cu diffusion and qualify the barriers. RESULTS AND DISSCUSSION Barrier Strength during Thermal Stressing The samples annealed at 500 o C show no evidence of Cu diffusion towards the Si substrate as shown in figures 2(a) and 2(b) for Ta and W based barriers respectively. After annealing at 650 o C, the Ta barrier shows evidence of Cu diffusion in the underlying CoSi and silicon regions. This result agrees with those in the literature, which demonstrated a 50nm PVD Ta barrier failed at 600 o C [2] when the barrier becomes discontinuous as a result of TaSi formation at the Cu interface [3]. In contrast, the W barrier remains effective at inhibiting Cu diffusion, with no Cu trace observed beyond the barrier. This suggests the Ti/TiN/W barrier is superior diffusion stop capability, although the Ta based barrier is adequate for the process temperatures achieved during processing. Barrier Stability during Electrical Stressing Figure 3 shows the results of the electromigration tests for the barrier/contact configurations studied. All samples using a W plug contact (split A) show little degradation after 1000 hours of EM E le ctro n flow 100 μm 0. 2 μ m Gate poly line Metal 1 line 100μm Top view S ide vie w FIGURE 1: SCHEMATIC DIRAGRAM OF THE TETS STRUCTURE SHOWING (A) TOP VIEW AND (B) SIDE VIEW TABLE 1: SPLIT PLAN ON CONTACT BARRIER AND SEED. “RSP” DENOTES THE DURATION OF AR+ RESPUTTER IN THE PVD SYSTEM Split Barrier type Note A 20nm Ti+20nm TiN+W Reference W CN B (PVD) 28nm Ta+0 sec rsp 80nm Cu Seed C (PVD) 28nm Ta+10 sec rsp 80nm Cu Seed D (CVD) 5nm Ti + 5nm TiN +15nm W 80nm Cu Seed FIGURE 2: SIMS DATA FOR (A) TA BARRIER SAMPLE AND (B) W BARRIER SAMPLE AFTER ANNEALS AT 500 O C AND 650 O C 677 978-1-4244-2050-6/08/$25.00 ©2008 IEEE IEEE CFP08RPS-CDR 46 th Annual International Reliability Physics Symposium, Phoenix, 2008 Authorized licensed use limited to: Newcastle University. Downloaded on March 16,2010 at 10:57:37 EDT from IEEE Xplore. Restrictions apply.