IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 12, DECEMBER 2008 2107 Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring Stephen M. Plaza, Igor L. Markov, Senior Member, IEEE, and Valeria M. Bertacco, Member, IEEE Abstract—The relatively poor scaling of interconnect in modern digital circuits necessitates a number of design optimizations, which must typically be iterated several times to meet the speci- fied performance objectives. Such iterations are often due to the difficulty of early delay estimation, particularly before placement. Therefore, effective logic restructuring to reduce interconnect de- lay has been a major challenge in physical synthesis, a phase dur- ing which more accurate delay estimates can be finally gathered. In this paper, we develop a new approach that enhances modern high-performance logic synthesis techniques with flexibility and accuracy in the physical domain. This approach is based on the following: 1) a novel criterion based on path monotonicity, which identifies those interconnects that are amenable to optimization through logic restructuring, and 2) a synthesis algorithm relying on logic simulation and placement information to identify placed subcircuits that hold promise for interconnect reduction. Experi- ments indicate that our techniques find optimization opportunities and improve interconnect delay by 11.7% on average at less than 2% wirelength and area overhead. Index Terms—Logic simulation, logic synthesis, physical synthesis. I. I NTRODUCTION A S INTERCONNECT contributes an increasingly signifi- cant fraction of overall circuit delay, the focus of design methodology is shifting from logic optimization to interconnect optimization. While this transition has been occurring for over a decade, meeting performance objectives is becoming more and more difficult. In recent years, a few successful methodologies achieved timing closure by combining netlist-level minimiza- tion in logic synthesis with postplacement physical optimiza- tions. This family of solutions is known as physical synthesis. Related strategies, including interconnect buffering [21], gate sizing [18], and relocation [1], successfully improved delay. In [8], [11], [17], and [32], postplacement resynthesis achieved delay improvement with limited placement perturbation, but these techniques are limited to simple signal substitution trans- formations. As the major portion of the critical delay is shifting into interconnect [38], poor design choices during synthe- sis cannot be easily corrected by limited-scale postplacement optimizations. Therefore, more accurate delay models have Manuscript received May 13, 2008; revised July 24, 2008. Current version published November 19, 2008. This paper was recommended by Associate Editor G.-J. Nam. The authors are with the Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI 48109-2121 USA (e-mail: splaza@umich.edu; imarkov@umich.edu; valeria@umich.edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCAD.2008.2006156 been developed to guide logic synthesis. Wire-load models that estimate delay by considering the capacitive load of each net were effective until wire capacitance and resistance be- came predominant. Further knowledge of the impact of place- ment on wirelength was consequently needed by synthesis algorithms. To meet the challenge of performance optimization at the 130-nm technology node and beyond, the traditional design flow transformed from several discrete optimization phases (such as logic synthesis followed by place and route) into a more holistic strategy. In [14], wirelength estimation was in- corporated in logic synthesis by constructing a highly placeable netlist with the goal of reducing wire detours. In addition, topographical information has been used to guide current syn- thesis tools [40]. Due to the importance and inherent diffi- culty of estimating the impact of placement and routing on interconnect, researchers suggested the idea of maintaining a companion placement estimate throughout the logic synthesis process [10], [15], [26]. However, interconnect-aware logic transformations are still limited by the accuracy of the estimates available. Furthermore, guiding logic synthesis by conservative delay estimates, as in [14], can lead to transformations that do not improve critical path delay but increase area and power consumption. While aggressive logic restructuring using global intercon- nect information can exploit better estimates later in the de- sign flow, such accounts have eluded published literature. One particular complication is that the limited amount of flexibil- ity found in combinational circuits must be combined with physical aspects of performance optimization. In this paper, we introduce a postplacement solution that enables aggressive optimization while minimizing changes to the physical netlist. We consider a wide range of changes to the circuit structure while also tracking their impact on physical parameters. Our contributions are as follows. 1) A novel metric for efficiently identifying nonmonotonic paths in the circuit, which locates regions where restruc- turing provides the greatest gains. This metric generalizes the metric in [4] and considers longer paths. 2) A generic and powerful technique for discovering logic transformations using functional simulation, which also facilitates fast reevaluation of physical parameters. Our technique does not require local equivalence between the optimized subcircuit and the original one but uses simulation and satisfiability to ensure that the circuit’s functionality is unmodified. 0278-0070/$25.00 © 2008 IEEE Authorized licensed use limited to: IEEE Xplore. Downloaded on February 3, 2009 at 12:40 from IEEE Xplore. Restrictions apply.