R. Loganya et al., International Journal of Emerging Trends in Engineering Research, 12(4), April 2024, 57 – 61 57 ABSTRACT Portable high speed digital devices are an emerging area and the designing of such circuits in VLSI is the need of the hour. Arithmetic and logic functions are the main blocks of such designs. Adders and subtractors are used in complex data processing to perform arithmetic operations. Designing of adders and subtractor using 6T XNOR demonstrates Low power, high speed switching and also optimized Area by means of transistor count compared to conventional adders and subtractors. This paper presents novel approach for 6T XNOR based full adder and full subtractor circuits. The circuit realization has been performed using DSCH and waveforms are obtained by using Micro wind 3.1 Key words: DSCH, Full Adder, Full Subtractor, Low Power, Micro wind 3.1, VLSI, 6T XNOR. 1. INTRODUCTION In many of the VLSI application we see the significant use of arithmetic operations. Most of the arithmetic and logic applications requires adders and subtractors as their primary component. Circuit realization for low area and power has become an important issue with the growth of integrated circuit. Minimum power and Minimum time delay are the main functions to design the logic for the VLSI Circuits. Minimizing the transistor in the design of full adders and full subtractors which forms the basic building blocks of all digital VLSI circuits has been undergoing to, minimizing the power consumption and increasing the speed Owing to the significant role that XNOR gates play in a variety of circuits, particularly arithmetic circuits, optimal XNOR circuit design is required to achieve low size and latency. The primary concern to design XNOR gate is to obtain low power consumption, delay and full output with low number of transistors to implement it. To improve various circuits, designers use different logic design techniques such as complementary MOS (CMOS), and pass transistor logic, GDI. Each of these methods has a unique design mechanism, along with some benefits and drawbacks. As we know that there are conventional CMOS are the traditional work horse for building digital circuits. The conventional adder uses different number of transistors to design Full adders and Full subtractors like 28T,16T,14T,10T,8T etc... are used for the implementation by using CMOS technique. Full adders and Full subtractors which has the least number of transistors has described to be the best design to achieve low power consumption. Reducing transistor count is a powerful technique for lowering power consumption in circuits. PTL and GDI both use fewer transistors compared to standard CMOS designs for adders and subtractors, this reduction in transistors leads to lower power consumption and known to increase the efficiency of area. Previous circuits are summarized and compared with our new approach. 2.EXISTING METHOD 2.1 14T Full Adder and Full Subtractor The Full Adder and Full Subtractor are designed using 14transistors. Here the circuits are implemented using XOR and XNOR and Multiplexer logic and these are designed using CMOS logic [5]. The schematic of 14T Full Adder and Full Subtractor are shown in Figure 1, Figure 2. Figure 1: 14T Full Adder Design of Novel Low Power 6T XNOR based Full Adder and Full Subtractor and Comparison of Various Adders and Subtractors R. Loganya 1 , B. Manisha 2 , CH. Jahnavi 3 , G. Jyothsna Devi 4 1 M..E, India, loganyabharani@gmail.com 2 B. Tech, India, manishabathini23@gmail.com 3 B. Tech, India, jaanuch7@gmail.com 4 B. Tech, India, jyothsnadevigoli1412@gmail.com Received Date: February 28, 2024 Accepted Date: March 27, 2024 Published Date : April 07, 2024 ISSN 2347 - 3983 Volume 12. No.4, April 2024 International Journal of Emerging Trends in Engineering Research Available Online at http://www.warse.org/IJETER/static/pdf/file/ijeter031242024.pdf https://doi.org/10.30534/ijeter/2024/031242024