International Journal of Power Electronics and Drive System (IJPEDS) Vol. 7, No. 3, September 2016, pp. 892~900 ISSN: 2088-8694, DOI: 10.11591/ijpeds.v7.i3.pp892-900  892 Journal homepage: http://iaesjournal.com/online/index.php/IJPEDS Investigation of the Common Mode Voltage for a Neutral-Point- Clamped Multilevel Inverter Drive and its Innovative Elimination through SVPWM Switching-State Redundancy C Bharatiraja 1 , JL Munda 2 , N Sriramsai 3 , T Sai Navaneesh 4 1,3,4 Department of Electrical and Electronics Engineering, SRM University, Chennai, India 2 Centre for Energy and Electric Power, Department of Electrical Engineering Tshwane University of Technology, South Africa Article Info ABSTRACT Article history: Received Nov 12, 2015 Revised Apr 1, 2016 Accepted May 2, 2016 The purpose of this paper is to provide a comprehensive Investigations and its control on the common mode Voltage (CMV) of the three-phase three-level neutral-point diode-clamped (NPC) multilevel inverter (MLI). A widespread space-vector pulse width modulation (SVPWM) technique to mitigate the perpetual problem of the NPC-MLI, the CMV, proposed. The proposed scheme is an effectual blend of nearest three vector (NTV) and selected three vector (STV) techniques. This scheme is capable to reduce the CMV without compromise the inverter output voltage and Total harmonics distraction (THD). CMV reduction achieved less than +Vdc/6 using the proposed vector selection procedure. The theoretical Investigations, the MATLAB software based computer simulation and Field Programmable Gate Array (FPGA) supported hardware corroboration have shown the superiority of the proposed technique over the conventional SVPWM schemes. Keyword: Common mode voltage (CMV) Field programmable gate array (FPGA) Neutral-point diode-clamped multi-level inverter (NPC-MLI) Space vector PWM (SVPWM) Copyright © 2016 Institute of Advanced Engineering and Science. All rights reserved. Corresponding Author: C Bharatiraja, Department of Electrical and Electronics Engineering, SRM University, Chennai, India. Email: bharatiraja@gmail.com 1. INTRODUCTION Recently, multilevel inverters (MLIs) have gained a lot of attention in the field of medium & high power applications [1]. Many pulse width modulation (PWM) techniques proposed in the literature [2] to control the MLIs. However, all PWM produces alternating common-mode voltages (CMVs) that create substantial problems in power drives. The alternating CMVs create significant common-mode current (CMC) leakage called as bearing current (ib), which may cause premature motor bearing failures [3-4]. CMV divided into two types of approaches: 1) full elimination (FE) and 2) partial elimination (PE) of CMV. There have been a number of techniques suggested for FE CMV and EMI eliminations. However, few of them have addressed the CMV directly and successfully [5-7]. However, PE method is still having lost challenging for further reduction of CMV. Hence, the researcher gears in this field to give the substantial. A solution to the CMV problem is to use passive filters [8-9] to reduce the CMV/CMC. The solution is to revise the PWM control strategy for the inverter to reduce the CMV have been reported for both carrier- based and SVM schemes [10-12], First, Kim et al. [7] propose PE by using carrier PWM for a three-level NPC-MLI. Due to the non-nearest vectors, the THD produced by this scheme is higher than conventional method. Mohan M.Range et al [13] has been compared CMV generation with Various SPWM methods like PD,POD,APOD verses various reductions, however the further reduction have not consider this paper. C.Bharatiraja, et al. [12] proposed a scheme whereby the minimal CMV sequence voltage for each level made Vdc/6 using PD and POD PWM schemes. However further elimination not noticed in this paper.