3D ReRAM Arrays and Crossbars: Fabrication, Characterization and Applications Gina C. Adam National Institute for R&D in Microtechnologies (IMT) Bucharest, Romania gina.adam@imt.ro Bhaswar Chrakrabarti, Hussein Nili, Brian Hoskins, Miguel A. Lastras-Montaño, Advait Madhavan, Melika Payvand, Amirali Ghofrani, Kwang-Ting Cheng, Luke Theogarajan, Dmitri B. Strukov Department of Electrical and Computer Engineering University of California, Santa Barbara, USA AbstractAs the rapid progress of memristor technology continues, multi-layer stacking of these crossbars is needed in order to maximize the use of vertical space and achieve the required density for high throughput applications. This work summarizes our efforts of designing and building three- dimensional monolithically integrated memristive arrays and crossbars, both standalone and onto CMOS chips. We discuss the fabrication and electrical characterization details of stand- alone and CMOS integrated ReRAM arrays and crossbars together with their use in experimental demonstrations of digital and analog applications such as three-dimensional stateful logic, hardware security primitives and dot-product operations. Keywords Three-dimensional (3D), crossbar, metal-oxide, analog, material implication, CMOS integration, security primitives I. INTRODUCTION $1.  DF #685.,=5*: -.>2,.; architecture [1] implemented using resistive switches is a promising candidate for energy-efficient hardware implementations of neuromorphic circuits and dense non- volatile memories. Several challenges, like the the thermal budget, yield and uniformity, have to be considered during the fabrication of such hybrid multi-stack systems. The memristors should have tight switching variations to achieve high performance circuits. There have been demonstrations of multi-layer crossbar circuits [2-3], but mostly targeted towards digital memories and showing limited characterization statistics. Sidewall vertical integration is a cost-effective stacking solution [4-5], but it has been shown so far only for small linear arrays, not crossbars, and is not entirely suitable for the CMOL architecture. Important steps have been made towards the hybrid integration of ReRAM technology with CMOS. There have been reports where memristors were fabricated between CMOS metal layers or onto CMOS chips [6-8], but they include limited discussions on the quality of the interface between the CMOS chip and the layers of resistive switches. Recently, in-memory computation capability was shown in 3D vertical resistive memory devices monolithically integrated with FinFET selectors [6]. However, successful demonstrations of CMOL circuits are still missing. This work summarizes our efforts of designing and building 3D monolithically integrated memristive crossbars, both standalone and onto CMOS chips, and further using them for prototyping promising applications. The paper is organized as following. Firstly, the fabrication details are presented in section II. Section III is dedicated to the electrical characterization. Lastly, in section IV, the applications implemented experimentally with these devices are presented, ranging from stateful logic, to physically unclonable functions (PUFs) and to dot-product operations. II. FABRICATION Firstly, we reported the fabrication of a small three- dimensional array of four bipolar ReRAM devices (Fig. 1a) [9]. The middle electrode was shared between bottom and top devices. The bottom devices were larger so as to prevent device failure due to misalignment and had an active area of 500 nm × 500 nm, while the the top devices an active area of 300 nm × 500 nm. All photolithography steps were done with an ASML DUV stepper. Three lift-off steps were used to pattern a) the bottom electrode deposited with e-beam metal deposition, b) the first active layer and the middle electrode deposited via sputtering and c) the second active layer and top electrode deposited via sputtering as well. A fourth photolithography was used to dry etch through the sacrificial SiO 2 in order to electrically contact the samples. The thermal budget of this process was 175°C and thus CMOS compatible. Three fabrication details were taken into consideration when designing the processing flow for these devices. Firstly, after extensive material engineering as previously reported in [10], optimized sub-stoichiometric TiO 2-x developed via reactive sputtering was chosen as the active material, together with a thin Al 2 O 3 barrier film to increase the non-linearity of the device. The TiO 2-x film had controlled stoichiometry by controlling the oxygen flow rate during the deposition. By depositing sub-stoichiometric films, it was possible to reduce the forming voltages of these devices as needed for the monolithic integration into working arrays and crossbars. Proceedings of the 17th IEEE International Conference on Nanotechnology Pittsburgh, USA, July 25-28, 2017 978-1-5090-3028-6/17/$31.00 ©2017 IEEE 844