ARTICLES https://doi.org/10.1038/s41928-018-0115-z 1 Electrical and Computer Engineering Department, University of California Santa Barbara, Santa Barbara, CA, USA. 2 School of Engineering, Hong Kong University of Science and Technology, Clear Water Bay, Kawloon, Hong Kong. *e-mail: mlastras@ece.ucsb.edu; timcheng@ust.hk R esistive random-access memory (ReRAM) based on two- terminal resistance-switching memristive devices is a prom- ising candidate to fill the gap between the main working memory and the storage in modern computing systems. ReRAM, a non-volatile memory (NVM) technology, offers memory densi- ties that are comparable to those of NAND flash, the leading NVM storage technology, and fast random accesses that are comparable to those of dynamic random-access memory, the de facto standard for main working memory 1 . ReRAM, therefore, effectively offers the advantages of both technologies. Three key attributes make mem- ristor-based ReRAM attractive compared to other NVM technolo- gies. First, shrinking the size of the two electrodes of the memristor will not degrade its key properties, such as retention, switching time and on/off ratio, as these properties are mainly determined by a single localized nanometre-scale filament. Second, the mem- ristor’s nonlinear switching dynamics allows removal of the access element (for example, a transistor) from the memory cell, which is beneficial in reducing the cell’s complexity and size, as the access element usually dominates its overall size. Third, a memristor has a simple metal–insulator–metal structure. The second and third attributes enable memristive devices to be organized into a high- density crossbar array. However, these same three attributes are also the sources of its biggest limitations: its filamentary nature leads to large device-to-device and cycle-to-cycle variations and the use of a crossbar array results in the sneak-path problem. In this Article, we report a ReRAM cell design and an informa- tion encoding scheme that together solve the sneak-path problem and greatly improve the tolerance of ReRAM to memristor varia- tions. The memory cell, which is termed an H3 cell, consists of two memristors and a minimum-sized transistor. We use the ratio of the resistances of the two memristors in an H3 cell to encode informa- tion, in contrast to the existing ReRAM architecture’s reliance on a single memristor’s absolute resistance to encode information. This results in much greater data reliability in the presence of sources of variation in memristors. Furthermore, our solution is comple- mentary to any device- and material-based solution. The proposed cell design and architecture can substantially enhance the benefits of any device-level improvement. Memristive devices and ReRAM architectures The fingerprint of a bipolar memristor is a pinched hysteresis loop in the current–voltage (I–V) plane 2 , as shown in Fig. 1a for a tita- nium oxide-based device. Physically, a memristor is a two-terminal device formed by two metallic electrodes sandwiching a thin layer of insulating material, as illustrated in Fig. 1b. As fabricated, a mem- ristor typically presents a very high resistance across its terminals (an unformed state) and an initial one-time electroforming step is needed. This is done by applying a voltage or current sweep across the device’s terminals until a soft breakdown of the thin insulating layer occurs, creating a conductive filament that brings the memris- tor into a low-resistance state (LRS) 3 . Changing the memristor from an LRS to a high-resistance state (HRS) requires a ‘reset’ operation, in which a voltage greater than a reset threshold V RESET is applied to partially destroy the conductive filament. The process of chang- ing the memristor from an HRS to an LRS, called a set operation, involves applying a voltage greater than a set threshold V SET to cre- ate the conductive filament again. The main memory element in a ReRAM unit cell is the memristor. Logic ‘1’ is written into a cell by setting its memristor to an LRS. Logic ‘0’ is written by resetting it to an HRS. The state of a memory cell is typically determined by apply- ing a small voltage across its memristor and comparing the resulting current against a reference current. We call this a ‘resistance-based current sensing’ approach. The crossbar architecture, illustrated in Fig. 1c, is the preferred ReRAM architecture from the density point of view. This is also known as the 1TnR architecture, as every electrode is connected to n memristors and one transistor is needed to access each elec- trode when reading from or writing to any of the n memristors. This architecture can achieve the smallest theoretical memory cell size, 4F 2 , when both the electrodes and the spaces between them are of width F. Writing to a device is typically done using the ‘V/3’ biasing scheme 4 , in which the required write voltage Resistive random-access memory based on ratioed memristors Miguel Angel Lastras-Montaño  1 * and Kwang-Ting Cheng  2 * Resistive random-access memories made from memristor crossbar arrays could provide the next generation of non-volatile memories. However, integrating large memristor crossbar arrays is challenging due to the high power consumption that origi- nates from leakage currents (known as the sneak-path problem) and the large device-to-device and cycle-to-cycle variations of memristors. Here we report a memory cell comprised of two serially connected memristors and a minimum-sized transis- tor. With this approach, we use the ratio of the resistances of the memristors to encode information, rather than the absolute resistance of a single memristor, as is traditionally used in resistive-based memories. The minimum-sized transistor, which is connected to the midpoint between the two series-connected memristors, is used to sense the voltage to read the state of the cell and to assist with write operations. Our memory cell design solves the sneak-path problem and, compared to the traditional resistance-based current sensing approach for memory reads, our ratio-based voltage sensing scheme is more robust and less prone to data errors caused by variations in memristors. NATURE ELECTRONICS | VOL 1 | AUGUST 2018 | 466–472 | www.nature.com/natureelectronics 466