Fusion Engineering and Design 88 (2013) 1332–1337 Contents lists available at ScienceDirect Fusion Engineering and Design jo ur n al hom epa ge: www.elsevier.com/locate/fusengdes Control and data acquisition ATCA/AXIe board designed for high system availability and reliability of nuclear fusion experiments A.J.N. Batista a,∗ , C. Leong b , V. Bexiga b , A.P. Rodrigues a , A. Combo a , B.B. Carvalho a , P.F. Carvalho a , J. Fortunato a , B. Santos a , P. Carvalho a , M. Correia a , J.P. Teixeira b , I.C. Teixeira b , J. Sousa a , B. Gonc ¸ alves a , C.A.F. Varandas a a Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade Técnica de Lisboa, 1049-001 Lisboa, Portugal b INESC-ID, Lisboa, Portugal a r t i c l e i n f o Article history: Available online 22 February 2013 Keywords: Fast control Data acquisition PCI express FPGA ATCA AXIe a b s t r a c t This paper describes the implementation and test of a control and data acquisition board designed to be integrated on systems demanding high availability and reliability, foreseen for future experiments like ITER or other long operation fusion devices. The Advanced Telecommunications Computing Architecture (ATCA) standard (PICMG 3.0 and 3.4) was selected for board implementation, which has support for the desired system robustness and performance. Some board features such as rear Input/Output (IO) signals connectivity (passive, copper tracks only), cable-less hot-swap maintenance, Intelligent Platform Man- agement Controller (IPMC) and redundancy on timing signals, communications links and power supplies are significant board improvements, relatively to previous control and data acquisition boards, allowing the development of more reliable system architectures. Moreover, the developed board is also compatible with the emerging ATCA eXtensions for Instrumentation (AXIe) specifications, which provides additional timing and synchronization signals on the backplane. ATCA full-mesh, multi-gigabit, full-duplex, point- to-point communication links between Field Programmable Gate Arrays (FPGA), of peer boards inside the shelf, allow the implementation of distributed algorithms and development of Multi-Input Multi- Output (MIMO) systems. Up to 48 analog input channels, simultaneously digitized (2 MSPS @ 18-bits), are filtered/decimated by the board FPGA and sent to the ATCA/AXIe host through Peripheral Component Interconnect express (PCIe) using Direct Memory Access (DMA). In real-time, the host can update up to 48 analog output channels (1 MSPS @ 18-bits), per board, through PCIe. Further board characteristics comprise analog IO channels with galvanic isolation and an optional signal chopper mode, for offset com- pensation over time on digital integration of magnetic signals. Board time synchronization is attained by means of the Inter-Range Instrumentation Group (IRIG) time-code. © 2013 Elsevier B.V. All rights reserved. 1. Introduction The development of the ITER Fast Plant System Controller (FPSC) prototype [1], by Instituto de Plasmas e Fusão Nuclear (IPFN), has instigated an in-house implementation of a control and data acquisition board (ATCA-IO-PROCESSOR) [2]. Future experimental fusion devices with large dimensions and long duration plasma discharges, e.g. tokamak ITER, are expected to have a large num- ber of signals from diagnostics, e.g. magnetics, and probably to require high levels of reliability and availability on their control and data acquisition systems. The implemented board was designed to respond to the upcoming fusion systems needs providing high ∗ Corresponding author. Tel.: +351 218 419 113; fax: +351 218 417 819. E-mail address: toquim@ipfn.ist.utl.pt (A.J.N. Batista). channel count on the analog Input/Output (IO), along with gal- vanic isolation, and an optional signal chopper mode for offset compensation over time if, as an example, digital integration of magnetic signals is required. Additionally, redundancy on power supplies, timing signals and communications links is achieved due to the board compliance with the Advanced Telecommunications Computing Architecture (ATCA) standard (PICMG 3.0 and 3.4) [3]. Coping with ATCA standard has also originated the development of an Intelligent Platform Management Controller (IPMC) [4] to board health monitoring, hot-swap management and hardware/firmware configuration. Another important board feature is the rear IO analog sig- nals connectivity, allowing cable-less hot-swap maintenance of the front board. Simultaneously, cabling connected to the passive (cop- per tracks only) Rear Transition Module (RTM) is preserved from physical movements. 0920-3796/$ – see front matter © 2013 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.fusengdes.2013.01.093