JOURNAL OF DISPLAY TECHNOLOGY, VOL. 9, NO. 12, DECEMBER 2013 1001 Transparent Current Mirrors With a-GIZO TFTs: Neural Modeling, Simulation and Fabrication Pydi Ganga Bahubalindruni, V´ ıtor Grade Tavares, Pedro Barquinha, Cândido Duarte, Pedro Guedes de Oliveira, Rodrigo Martins, and Elvira Fortunato Abstract—This paper characterizes transparent current mir- rors with n-type amorphous gallium–indium–zinc–oxide (a-GIZO) thin-film transistors (TFTs). Two-TFT current mirrors with dif- ferent mirroring ratios and a cascode topology are considered. A neural model is developed based on the measured data of the TFTs and is implemented in Verilog-A; then it is used to simulate the circuits with Cadence Virtuoso Spectre simulator. The simulation outcomes are validated with the fabricated circuit response. These results show that the neural network can model TFT accurately, as well as the current mirroring ability of the TFTs. Index Terms—Transparent current mirrors, amorphous gallium–indium–zinc–oxide thin-film transistor (a-GIZO TFT), neural modeling. I. INTRODUCTION A MORPHOUS gallium–indium–zinc–oxide (a-GIZO) thin-film transistor (TFT) technology has potential in- dustrial applications in large-area, low-cost transparent display technologies such as AMOLED [1] and ultra definition LCD [2]. Fabrication can be achieved at low temperature, followed by heat treatment not exceeding 200 C. Furthermore, the high electrical mobility 20 cm /V s [3] compared to other TFTs (a-Si:H : 1 cm /V s [4], organic TFT : 0.1-–1 cm /V s [5]), make a-GIZO TFTs attractive for transparent and flexible electronics [6]. These are the motivating factors to build analog circuits for various types of sensing and display applications, which will be portable and economic, resulting in integrated circuits that avoid interfacing problems. The analog circuit design is limited due to the lack of stable p-type TFT and unavailability of built-in libraries for the active and passive Manuscript received May 04, 2013; revised July 01, 2013; accepted July 17, 2013. Date of publication July 30, 2013; date of current version November 18, 2013. This work was supported by the ERDF through the Programme COMPETE and by the Portuguese Government through FCT—Founda- tion for Science and Technology under Projects CMU-PT/SIA/0005/2009, FCOMP-01-0124-FEDER-013070, and PEST-C/CTM/LA0025/2011 strategic project, and also by the European Research Council through the Advanced Grant INVISIBLE (ERC-2008-AdG 228144. The work of P. G. Bahubalin- druni and C. Duarte is also supported in part by the FCT under Grants BD/62678/2009 and BD/28163/2006, respectively. P. G. Bahubalindruni, V. G. Tavares, C. Duarte, and P. G. de Oliveira are with INESC TEC (formerly INESC Porto) and Faculty of Engineering, University of Porto, Campus FEUP, 4200-465 Porto, Portugal e-mail: (vgt@fe.up.pt). P. Barquinha, R. Martins, and E. Fortunato are with CENIMAT/I3N, Depart- ment of Materials Science, Faculty of Science and Technology, FCT, Universi- dade Nova de Lisboa, and CEMOP-UNINOVA, 2829-516 Caparica, Portugal. Color versions of one or more of the figures are available online at http:// ieeexplore.ieee.org. Digital Object Identifier 10.1109/JDT.2013.2275251 components. Nevertheless, few circuits are reported, mostly with depletion type TFTs such as a shift register [7] and a 6-bit current-steering DAC [8]. In order to design and simulate circuits, punctilious device models are necessary to predict the device behavior during sim- ulations. Models based on device physics are generally used for circuit design. Nevertheless, physical models are complex and time consuming to develop. Especially physical modeling is not a good choice for novel technologies, such as a-GIZO, which are not yet well matured, and where experiments are still going on to ensure better behavior, either by changing device structure [9], materials for electrodes or processing conditions. All these factors certainly impact the density of states and charge carrier flow in the device. Whenever there is a change in any of the aforementioned factors, the corresponding device physics need to be studied and a new model needs to be developed. Possible alternative methods are table-based and neural network models that are built from the device measured characteristics. How- ever, accurate table-based models [10] demand huge memory. Artificial Neural Network (ANN) modeling overcomes all these drawbacks without compromising performance. When quicker circuit design is important, with new devices as a-GIZO TFT, a simple, accurate and continuous model, with less development time is desired. ANNs have all these properties, and in fact, multilayer feedforward network has already been successfully applied to model MOSFETs, as proposed in [11]. The current work includes the complete device behavior, i.e., intrinsic and extrinsic, by taking the series resistance of source and drain electrodes into account. If only the intrinsic behavior of the device needs to be modeled, the impact of should be deembeded from the measured data. Then, the network needs to be trained with this new data. The extraction method of should basically follow the same procedure as in physical mod- eling. General steps in physical and ANN based modeling ap- proaches are shown in Fig. 1. Current mirrors are important functional blocks in analog cir- cuit design, which find applications in providing bias, as an ac- tive load and pixel driving circuits in OLED displays [12]. ZTO TFT-based current mirrors have been already reported in the past, but with metallic electrodes and requiring a high post-pro- cessing temperature of 400 C [13]. In this work we are re- porting simple current mirrors with two TFTs having different mirroring ratios and a cascode mirror, all based on fully trans- parent GIZO-TFTs with processing temperatures not exceeding 200 C. As a first step, an ANN model is developed from the measured data of the TFTs, being then implemented in Ver- ilog-A for circuit simulation using Cadence Virtuoso Spectre. 1551-319X © 2013 IEEE