Sub-5V Germanium Waveguide Avalanche Photodiode based 25 Gb/s 1310 nm Optical Receiver H. T. Chen, 1,2,* J. Verbist, 2,3 P. Verheyen, 1 P. De Heyn, 1 G. Lepage, 1 J. De Coster, 1 P.Absil, 1 B. Moeneclaey, 3 X. Yin, 3 J. Bauwelinck, 3 J. Van Campenhout, 1 and G. Roelkens 2 1 Interuniversity Microelectronics Center (IMEC), Kapeldreef 75, 3000 Leuven, Belgium Hongtao.Chen@imec.be 2 Photonics Research Group, Department of Information Technology, Ghent University - imec, B-9000 Ghent, Belgium. 3 Design Research Group, Department of Information Technology, Ghent University – iMinds – IMEC, B-9000 Ghent, Belgium. Abstract: We demonstrate low-voltage waveguide-coupled germanium avalanche photodetectors (APDs) with a gain×bandwidth product of 140 GHz at -5 V. An optical receiver based on such an APD operating up to 25 Gb/s is demonstrated. OCIS codes: (040.1345) Avalanche photodiodes (APDs); (040.5160) Photodetectors; (200.4650) Optical interconnects. 1. Introduction Integrated germanium avalanche photodetectors (APDs) offer great potential to improve the link budget of silicon- based optical interconnects. Low operation voltage is the key design target for the CMOS compatible Ge APDs. In [1,2], we demonstrate a 10Gb/s 1550nm silicon photonics optical receiver based on a Ge waveguide vertical p-i-n APD. A 5.8dB avalanche sensitivity improvement was obtained at a low APD bias voltage of -5.9V inferred from bit error ratio measurements. In this paper, by engineering the Ge APD design, a 10Gb/s 1310nm optical receiver is demonstrated showing 7dB sensitivity improvement at a low APD bias of -4.85V. A 20Gb/s 1310nm silicon photonics optical receiver based on such a Ge APD showing 6.2dB sensitivity improvement at -5.0V APD bias, and operation of the receiver up to 25Gb/s is demonstrated. The wafer-scale mean gain*bandwidth product value is 140GHz at -5V bias voltage (a 3dB bandwidth of 15.2GHz at the avalanche gain of 9). 2. Device Design and Fabrication The Ge waveguide APDs, as shown in Fig. 1(a), were fabricated in imec’s fully integrated Si Photonics platform going through a process flow described in [3]. The Ge layer dimensions and doping configuration are shown in Fig. 1(b). A vertical p-i-n structure (VPIN) is formed by implanting Si with phosphorous ions (before Ge growth) and by implanting the planarized Ge layer with boron ions. A 185nm thin Ge layer was adopted to lower the operation voltage of the Ge APDs. The simulated doping distribution is shown in Fig. 2(a). The heterogeneous Ge/Si VPIN configuration with the 185nm thin Ge layer results in a strongly non-uniform electric field at -3V bias voltage as shown in Fig. 2(b), mostly confined in the lower 100nm of the Ge layer. Fig. 2(c) shows the electric field profile along A-A’ (in Fig. 2(b)) for a Ge layer of 185nm, 285nm and 385nm thick, respectively, at -3V bias voltage (assuming the same implant conditions). It can be seen that the thinner the Ge layer, the stronger the electric field is in the Ge layer. For the case of a 185nm-thick Ge layer, the electric field strength is calculated to be as high as 5.2×10 5 V/cm at the Ge/Si interface at a bias voltage of -3V. Fig. 1. (a) Schematic of the Ge waveguide APD. (b) Cross section of the Ge waveguide APD with Ge layer dimensions. (c) SEM cross-section image of the Ge waveguide APD. Fig. 2. (a) Simulated doping distribution in the Ge APD. Boron ion implantation in the Ge layer is generated from Monte-Carlo simulation. Only half of the structure is shown for clarity. (b) Simulated electric field distribution in the Ge layer at -3V bias. (c) Electric field profiles along A-A’ cut in the Ge APD at -3V bias.