Sixth-order programmable bandwidth bandpass sigma–delta modulator implemented with transmission lines L. Herna ´ndez, E. Prefasi and P. Rombouts An implementation of a sixth-order bandpass continuous time sigma– delta modulator using transmission lines is presented. A single tuning coefficient allows the exchange of resolution and bandwidth in this modulator, owing to the use of a two path transformation that exploits the similarity between transmission line modulators and discrete time modulators. The modulator tolerates two clock cycles of excess loop delay and a high clock jitter. Introduction: The coexistence of different communication standards in wireless systems demands new data converter architectures that allow reconfiguration to exchange bandwidth by resolution. Two common ADC converter architectures for digital receivers are pipe- line converters and continuous time sigma–delta modulators (CTSD) [1]. The coefficients of the loop filter of a CTSD modulator are dictated by the sampling period, which complicates bandwidth programmability by changing the clock frequency. Alternatively, pipeline converters do not employ noise shaping and, hence, cannot improve significantly their resolution by oversampling signals of different bandwidths. We present a bandpass sigma–delta modulator that benefits from the hardware implementation of continuous time modulators while preser- ving the advantages of discrete time modulators (DTSD), such as reduced jitter sensitivity. This modulator is based on similar principles to the lowpass modulator described in [2] and uses transmission lines as delay elements. The novelty of the modulator presented here, compared to [2], is the use in the design of its equivalent discrete time NTF of a z 1 to z 2 transformation, known as two-path transformation [3]. This allows us to trade off analogue signal bandwidth by resolution with a single tuning coefficient. As an additional benefit, the modulator tolerates two full clock periods of excess loop delay and a higher clock jitter level than conventional continuous time band pass modu- lators. Note that an N-path transformation is feasible in a delay-based CTSD modulator [2] owing to its formal similarity to discrete time modulators. An equivalent approach is not easily feasible in continuous time modulators based on lumped elements. Fig. 1 Prototype NTF pole-zero plots a Pole-zero plot of NTF(z) prototype used in design b Effect of replacing z 1 by z 2 in the NTF Design: Fig. 1a depicts the pole-zero plot of the NTF(z) prototype that will be used in the design. This transfer funcion has two complex conjugate zeros located in the unit circle close to a real zero at z ¼1. The phase  f of the two complex conjugate zeros will define the bandwidth of interest of the modulator and will be selected according to the desired oversampling ratio R. The NTF has been equipped also with three poles p 0 , p 1 and p* 1 to provide stability in a single bit design. If we replace z 1 by z 2 in the NTF, the zeros and poles are shifted around z ¼ e p=2 and the order is doubled, as shown in Fig. 1b, without an increase in the resonator count. The expression for the NTF represented in Fig. 1 is as follows: NTFðzÞ¼ ðz 2 þ 1Þðz 4  2 cosðfÞz 2 þ 1Þ ðz 4 þ az 2 þ bÞðz 2  cÞ ð1Þ The next step in the design is to accomplish the block diagram of a delayed system [2] with an equivalent behaviour to the proposed discrete time modulator. We may implement such a retarded system by means of transconductors, transmission lines, a sampler and quan- tiser and two current feedback DACs. The proposed system is shown in Fig. 2, where all transmission lines TL are identical, have a character- istic impedance Z 0 , an electrical delay T corresponding to the sampling frequency period f s ¼ 1=T , and a loss parameter A  1. It may be shown that any of the state variables u i comply with the following relationship U i ðsÞ¼ R i þ Z 0 1  Ae s2T 1 þ Ae s2T   I i ðsÞ ð2Þ Considering the system equivalence defined in [2], we may replace e s2T by z 2 in (2) and compute the corresponding NTF and STF of the modulator as if it were a discrete time system. Note that the equivalence in [2] holds for any DAC pulse shape of finite duration T , because the value of the DAC pulse in the sampling instant is what is relevant instead of the pulse area, as opposed to a conventional CTSD. We will select a NRZ zero-order-hold pulse which will desensitise the modulator against clock jitter and excess loop delay, owing to its constant value over the sampling period. To complete the design, it suffices to equate the coefficients of (1) with the NTF(z) obtained using Fig. 2 and (2) (assuming A ¼ 1) and the proposed replacement. Transconductances g m1 , g m2 and g m3 may be considered design para- meters to scale the state variables u i (t) and the STF gain. Table 1 shows the resulting design equations. Fig. 2 Block diagram of modulator Table 1: Design equations dac 1 ¼ 1  b þ ac  2 cos 2 ðfÞþðbc  a þ cÞ cosðfÞ 2Z 3 0 g m2 g m3 ð2 cosðfÞ 1  cos 2 ðfÞÞ dac 3 ¼ 3  a  b þ c þ bc þ ac  4 cosðfÞ 4Z 0 ðcosðfÞ 1Þ R 1 ¼ Z 0 ð2 cosðfÞ c þ bc þ aÞðcosðfÞ 1Þ 1  b þ ac  2 cos 2 ðfÞþðbc  a þ cÞ cosðfÞ R 2 ¼ 0 R 3 ¼ Z 0 g m12 ¼ 1 þ cosðfÞ Z 2 0 g m2 ð1  cosðfÞÞ Fig. 3 FFT of time domain simulations with different values of g m12 aR ¼ 16 bR ¼ 128 cR ¼ 256 The signal bandwidth of the modulator depends on angle f and can be modified by transcondutance g m12 , which moves four of the zeros of Fig. 1b all together, as shown by the arrows. Setting constant values for ELECTRONICS LETTERS 9th December 2004 Vol. 40 No. 25