Continuous time SD modulator based on digital delay loop and time quantisation L. Herna ´ndez and E. Prefasi A new sigma delta (SD) modulator suitable for ultra-low power data converters is introduced. The proposed architecture is based on time encoding and quantisation using voltage controlled delays such as digital inverters. The delays together with a phase comparator implement a synchronous pulse width modulator (PWM) and a discrete time integrator. An additional analogue integrator provides second- order noise shaping and compensates the nonlinearity of the digital delay. Time quantisation of the two-level PWM signal allows imple- menting a multibit modulator without requiring linear multibit DACs. Introduction: Ultra-low power data converters have been reported using voltage controlled oscillators (VCOs), showing first-order noise shaping [1]. The main limitation of such ADCs is the nonlinearity in the voltage- to-delay conversion inherent to starved digital inverters [1]. This limit- ation has been mitigated by supplementing the VCO with analogue in- tegrators and multibit feedback DACs [2]. VCO linearity has also been improved by calibration techniques [3]. Other delay based architectures [4] have been proposed as efficient time encoding ADCs. In this Letter, we propose an oversampled ADC based on a synchronous pulse width modulator (PWM). The PWM is implemented with variable digital delays (starved inverters). The pulse width information is extracted by a phase comparator and fed back into the delay control voltage, as a difference to [4]. Compared to VCO ADCs, in our approach there is no FM signal that could produce intermodulation products. The pro- posed architecture may achieve low power consumption and small area owing to the use of mostly digital circuits, making it suitable for sensor and biomedical applications. Delay based integrator: Fig. 1 depicts the block diagram of the integ- rator used in the proposed modulator. A sampling clock, clk, of fre- quency f s and period T s ¼ 1/f s , is applied to a variable delay (VD) element composed of N equal digital delay cells, generating output A. The instantaneous delay per cell will be proportional to control voltage V c (t), assumed to vary between 21 and 1. The total delay T[n] introduced by VD in the edges of the nth clock cycle can be approximated for large N by the solution of the following equation: N =  nTs +T [n] nTs dt T F + T v V c (t) (1) T F is the nominal delay of each delay cell and T V is a gain coefficient for V c (t). V c (t) is sampled by sampler S and held constant during each sampling period. Then, if N(T F + T V ) ≤ Ts, the solution of (1) will be: T [n]= NT F + NT V V c (nT s ) (2) FD VD D Q CL + – D Q CL ‘1’ ‘1’ clk F V c (t) x(t) PWM A B V(t) H(s) clk S w(t) Fig. 1 Delay controlled integrator Clock, clk, is also applied to a fixed delay (FD) of nominal value NT F , generating signal B. Signals A and B are applied to a phase comparator, outlined as F in Fig. 1. The phase comparator output, v(t), will be a pulse width modulated signal with one pulse of constant amplitude V d per sampling period, either positive or negative. The width of each pulse will be a sample of sequence w[n]. This sequence can be generated by applying v(t) to a sinc filter with transfer function H(s) that integrates v(t) over one sampling period and whose output will be sampled by S: H (s)= 1 − e −sTs sT s , h(t)= L −1 (H (s)) w[n + 1]= h(t)∗ v(t )| t=(n+1)Ts = 1 T s  (n+1)Ts nTs v(t) dt = V d T s (T [n]− NT F ) (3) By adding signal x(t) at the input and setting NV d T V T s 21 ¼ 1, we obtain the equation of a discrete time integrator: w[n + 1]= V d T V N T s V c (nT s )= x(nT s )+ w[n] (4) Second-order modulator: Fig. 2a shows a hybrid second-order sigma delta (SD) modulator which mixes continuous and discrete time integ- rators. Fig. 2b shows an equivalent system to the modulator of Fig. 2a, where int1 is represented by integrator I 0 . Integrator int2 is implemented with the integrator of Fig. 1. The transfer function of sinc filter H 1 is equal to H(s) (3) and consists of a delay and integrator I 1 . As long as PWM signal v(t) conveys information in the pulse width rather than in the amplitude, it may be quantised by sampling with a flip flop and a clock of frequency f Q . f s . To implement a 2 M level quan- tiser we need that: f Q = Mf s (5) a b clk x(t) y[n] fs s z –1 1–z –1 int1 int2 Q y a1 y a1 y a2 y a2 x(t) fs s I0 I2 Vc(t) PWM A B clk F D Q counter y[n] fQ v(t) 1–e –sT fs s I1 H1 u(t) 1-e -sT fs s H2 fQ w Fig. 2 Hybrid second-order modulator The time quantised signal u(t) can be directly converted into amplitude by another sinc filter H 2 , which produces feedback signal y a2 . A direct connection from u(t) can be used for y a1 , as long as it is fed directly into I 0 and hence only the area of u(t) during Ts is of relevance. A digital counter measures the pulse width of u(t) to generate a multibit digital output y[n]. Fig. 3 shows a simplified implementation of Fig. 2b. By moving I 1 and I 2 to the feed forward path and collapsing them with I 0 , only one analogue integrator is needed. The delay required in H 1 is accomplished by cascading inverter based digital delays T A and T B with FD and VD such that T A ¼ T B ¼ T S . Signals y a1 and y a2 are combined by a discrete delay z 2M and an adder to generate y a . As a result, most of the modulator hardware is digital circuitry. x(t) fs s Vc(t) PWM A B clk TA TB F1 F2 D Q counter fQ fQ v1(t) v2(t) y[n] z –M 2 DAC DAC analogue digital logic u(t) w y a Fig. 3 Simplified modulator Simulations: To verify the validity of this modulator, time domain simulations have been performed using a behavioural model of Fig. 3. Delays T A ,T B , VD and FD have been modelled as a chain of N ¼ 32 inverters each. For VD, the V dd of the inverters is controlled by V c (t). ELECTRONICS LETTERS 9th December 2010 Vol. 46 No. 25