Hybrid Hardware-Software Architecture for Reconfigurable Real-Time Systems ∗ Rodolfo Pellizzoni and Marco Caccamo Department of Computer Science, University of Illinois at Urbana-Champaign {rpelliz2, mcaccamo}@uiuc.edu Abstract Recent developments in the field of reconfigurable SoC devices (FPGAs) will enable the development of embedded systems where software tasks, running on a CPU, can coex- ist with hardware tasks. We devised a real-time computing architecture that can integrate hardware and software exe- cutions in a transparent manner, and can support real-time QoS adaptation by means of partial reconfiguration of mod- ern FPGA devices. Tasks are allowed to migrate seamlessly from CPU to FPGA and vice versa to support dynamic QoS adaptation and cope with dynamic workloads. In this pa- per, we discuss the design and implementation of an on-chip infrastructure, OS extensions and task design methodology that enable hardware-software transparency in the presence of relocation. The overall architecture is suitable to sched- ule real-time workloads and we derive bounds on reloca- tion overhead. Finally, we show the applicability of our de- sign methodology on a concrete task design case. 1. Introduction Recently emerging SoC devices enable the development of embedded systems where software tasks, running on a CPU, can coexist with hardware tasks running on a re- configurable device (FPGA). Such hybrid platforms are es- pecially suitable for the development of real-time embed- ded systems because they combine the flexibility of soft- ware execution on a CPU with timing predictability and high performance of hardware execution on a Partially Re- configurable Device (PRD). Even if the theory of real- time reconfigurable computing is still at an early stage [9, 10, 12, 11, 26], progresses have been made recently in the development of operating systems for reconfigurable de- vices (OSRD) [22, 30, 31]. OSRDs will enable a highly dy- namic use of partially reconfigurable FPGAs, running mul- ∗ This material is based upon work supported by NSF under Awards No. CNS0237884, CNS0720512, CCF0325716. Any opinions, find- ings, and conclusions or recommendations expressed in this publica- tion are those of the authors and do not necessarily reflect the views of the NSF. tiple concurrent circuits (hardware tasks) with full multi- tasking capabilities. In this work, we focus our attention on embedded sys- tems comprised by a general purpose CPU and a Partially Reconfigurable Device (PRD), together with main memory and I/O peripherals. Modern devices, like the Xilinx Virtex family of FPGA [33], implement all of the above on a sin- gle configurable SoC. Compared to a classic mono or multi- processor platform, hardware execution of real-time logic functions (tasks) on FPGA fabric has two main advantages: 1) it can greatly improve QoS and 2) it natively supports both temporal isolation (due to parallel execution on distinct reconfigurable regions) and temporal predictability (due to the precise knowledge of execution times). At the same time, implementing all system functionalities in hardware is not desirable for several reasons. First of all, it precludes reuse of already available software libraries and tasks. Sec- ond, some control heavy tasks are hard to parallelize and their hardware implementations yield low speedup. Third, some system tasks require little computation and can be ex- ecuted on a CPU with low utilization while they would con- sume precious FPGA area if implemented in hardware. The main objective of our research is to devise a real-time com- puting infrastructure that can integrate hardware and soft- ware execution in a transparent manner, and can support real-time QoS adaptation by means of partial reconfigura- tion of modern FPGA devices. In particular, flexibility of execution is achieved by supporting the seamless migra- tion of tasks from software to hardware and vice versa at run-time. Task migration enables the system to proritize dif- ferent types of computation based on environmental factors and to cope with different operational modes at run-time. While in this paper the proposed hybrid real-time comput- ing infrastructure has been mainly tested (see test case of Section 5) for achieving dynamic QoS adaptation and hard- ware predictability, we are also in the progress of exploiting it for real-time fault-tolerant computing. A lot of work has been done in the design of SoC com- munication infrastructure and in the development of work- ing prototypes for OSRD, but much more remains to be done to obtain a feasible and usable platform when real- time execution and on-line reconfiguration are considered. In a previous work [26], we have addressed the problem IEEE Real-Time and Embedded Technology and Applications Symposium 1080-1812/08 $25.00 © 2008 IEEE DOI 10.1109/RTAS.2008.14 273 IEEE Real-Time and Embedded Technology and Applications Symposium 1080-1812/08 $25.00 © 2008 IEEE DOI 10.1109/RTAS.2008.14 273 IEEE Real-Time and Embedded Technology and Applications Symposium 1080-1812/08 $25.00 © 2008 IEEE DOI 10.1109/RTAS.2008.14 273