Leveraging the Manycore Architecture of the Loihi Spiking Processor to Perform Quasi-Complete Constraint Satisfaction Chris Yakopcic 1* , Nayim Rahman 1 , Tanvir Atahary 1 , Tarek M. Taha 1 , Scott Douglass 2 1 Dept. Of Electrical and Computer Engineering, University of Dayton, Dayton, OH, USA 2 Human Effectiveness Directorate, Air Force Research Laboratory, Wright Patterson Air Force Base, OH, USA * cyakopcic1@udayton.edu Abstract—In many cases, low power autonomous systems need to make decisions extremely efficiently. However, as a problem space becomes more complex, finding a solution quickly becomes nearly impossible using traditional computing methods. Thus, in this work we show that constraint satisfaction problems (CSPs) can be solved quickly and efficiently using spiking neural networks. Constraint satisfaction is a general problem solving technique that can be applied to a large number of different applications. To demonstrate the validity of this algorithm, we show successful execution of the Boolean satisfiability problem (SAT) on the Intel Loihi spiking neuromorphic research processor. In many cases, constraint satisfaction problems have solution sets as opposed to single solutions. Therefore, the manycore architecture of the Loihi chip is used to parallelize the solution finding process, leading to a quasi-complete solution set generated at extreme efficiency (dynamic energy as low as 8 micro joules per solution). Power consumption in this spiking processor is due primarily to the propagation of spikes, which are the key drivers of data movement and processing. Thus, the proposed SAT algorithm was customized for spiking neural networks to achieve the greatest efficiency gains. To the best of our knowledge, the work in this paper exhibits the first implementation of constraint satisfaction on a low power embedded neuromorphic processor capable of generating a solution set. In general, we show that embedded spiking neuromorphic hardware is capable parallelizing the constraint satisfaction problem solving process to yield extreme gains in terms of time, power, and energy. Keywords—Spiking neural networks, Intel Loihi, neuromorphic hardware, constraint satisfaction, SAT I. INTRODUCTION Autonomous systems are being increasingly utilized in a variety of domains, including both mobile systems (UAVs, cars, and robots) as well as planning systems. In these systems, autonomous decision making must be performed at high speed in many cases. Thus, traditional algorithms like exhaustive search are no longer viable when time is of supreme importance. Similarly, traditional commercial computing systems may be abandoned for more exotic embedded architectures when size, weight, and power limitations are of supreme importance. Embedded spiking neuromorphic hardware [1-3] is a promising technology for the advancement of low power, portable, high efficiency processing. In spiking neural network (SNN) hardware, spikes are used to propagate information between neural network layers and cores. This is an extremely efficient design, as most energy is expended only when information is being processed [1,2]. However, to utilize SNN hardware at maximum efficiency, algorithms must be developed to take advantage of this unique hardware platform. In this work we propose a method for using the Intel Loihi manycore neuromorphic processor to solve, as well as parallelize, constraint satisfaction problems (CSPs). The presented work implements a subset of CSP known as the Boolean Satisfiability problem (SAT), which is a well- known combinatorial problem that determines whether a certain formula represented in Conjunctive Normal Form (CNF) is satisfiable [4]. CNF representation is basically the conjunction (AND) of several short clauses and each clause is a disjunction (OR) of Boolean variables (or literals). The entire formula is considered to be satisfiable if all the clauses in that formula are satisfied. This means at least one of the literals in each clause must evaluate to ‘true.’ SAT problems are considered one of the most fundamental problem types within mathematical logic, reasoning, machine learning, and many other theoretical domains [5], and they have the potential to be extremely computationally expensive [6]. Therefore, in this work we aim to alleviate this computational expense by presenting a method for solving SAT problems using SNNs. We utilize the Intel Loihi SNN processor to verify the proposed algorithm experimentally by executing different SAT scenarios. We leverage the manycore architecture of the Loihi chip to implement many SAT solvers in parallel. Each parallel solver executes with different initial conditions; thus each parallel solver has a high likelihood of converging to a different solution. We show this proposed manycore SAT implementation is capable of generating solution sets at extreme energy efficiency. In many applications of the SAT algorithm, solution sets are very attractive as multiple solutions can then be ranked against different criteria to determine the best path forward. To the best of our knowledge, this work represents one of the first implementations of SAT on embedded neuromorphic 978-1-7281-6926-2/20/$31.00 ©2020 IEEE