Molecular Dynamic Simulation Study of Stress Memorization in Si Dislocations Tzer-Min Shen, Yen-Tien Tung, Ya-Yun Cheng, Da-Chin Chiou, Chia-Yi Chen, Ching-Chang Wu, Y. M. Sheu, Han-Ting Tsai, C.M. Huang, G. Hsieh, Gino Tsai, Samuel Fung, Jeff Wu, Carlos H. Diaz Research and Development, Taiwan Semiconductor Manufacturing Company (TSMC) Hsinchu Science Park, Hsinchu County, Taiwan, Email: tmshen@tsmc.com Abstract Stress-Memorization-Technique by Si dislocations is effective in enhancing NFET device performance [1,2]. For the first time, MD (Molecular Dynamic) simulations are applied to explain the formation mechanism of dislocations during the Solid-Phase-Epitaxy-Regrowth (SPER) process. A semi- empirical TCAD method based on lattice-KMC (L-KMC) is then developed to predict dislocation formation. The simulated dislocation positions agree well with silicon experiments characterized by TEM. TCAD simulations show that the resulting dislocations are along the [111] direction and provide ~650MPa average longitudinal stress in channel regions, consistent with Nano-Beam-Diffraction (NBD) strain measurement. The channel stress is predicted by simulation to further increase by 1.5X after the poly-silicon gate removal step in a replacement-gate process. The dislocation SMT enhances NFET electron mobility by 25% and Ion-Ioff performance by 15%. Introduction Stress-Memorization-Technique (SMT) was proposed in poly-SiON gate processes to improve electron mobility for NFET in recent years [1,2]. The channel stress enhancement by poly-SiON SMT was attributed to the deformation of both the poly-Si gate and the amorphized S/D regions, well modeled by a plastic strain model [3,4]. However, this type of SMT, when applied in HK/MG process, becomes ineffective, because of the final absence of poly-gates and diminishing SD areas due to poly-pitch scaling. A modified SMT was reported, in which stacking fault defects were shown to form on (111) plane during the SPER process with a capping stressor film [1,2]. However, previous modeling works only focused on quantifying the stress level from given dislocations and the resulting performance benefit for nFETs. In this paper, for the first time, the fundamental dislocation formation mechanism is addressed. Predictive TCAD models are established for prediction of the location of the resulting defects in silicon, critical for NFET performance optimization. Process and SPER Modeling A schematic SMT simulation flow is shown in Figure 1. A pre-amorphization implant is used to create amorphous regions, followed by a stress capping film and thermal anneal. A stress film deposited at gate edge will induce compressive longitudinal stress in the amorphous region, as shown in Figure 2. During the annealing process, amorphous region is crystallized, SPER occurs and (111) plane stacking defects form. A microscopic view of the re-crystallization process is illustrated in Figure 3. To form perfect crystal bonds at the amorphous / crystal interface, different Si atoms cluster are needed on (100), (110) and (111) interfaces. Thus SPER rates on different amorphous / crystal (a/c) interface orientations differ. Applied stress during SPER distorts silicon lattice and affects bonding lengths, thus influencing SPER rate. Lattice-KMC [5] is used to simulate SPER and the progression of amorphous/crystal interface fronts. After model calibration, the a/c-Si interface fronts can be accurately predicted by Lattice-KMC. SMT dislocation formation was experimentally studied and linked to the merging of (100) and (110) crystal growth fronts. The simulated a/c growth fronts during SPER are shown in Fig.4. The angle between (100) and (110) growth fronts, θ, is used to predict defect formation. When the two growth fronts meet and form an acute angle (θ≦ 90° ), an edge dislocation is created. The dislocation depth and position, estimated by LKMC match well to literature data [6,7] in Fig. 5 and the simulated a/c fronts during SPER are shown in Fig. 6. Molecular Dynamic Simulation To understand the SMT dislocation formation mechanism, a rectangular amorphous Si lattice structure is studied by Molecular Dynamic (MD) simulation. The time period when an acute angle forms between the two growth fronts is simulated, as shown in Figure 7. Under no external applied stress, the simulation shows no dislocation formation as in Figure 8. However, when large enough external compressive stress is applied during SPER process, an edge dislocation and (111) plane stacking defects would form, as shown in Figure 9. It can be reasoned that the external compressive stress distorts silicon lattice, resulting in the 5-rings bonded Si atoms instead of 6-rings, as shown in Figure 10. The 5-rings Si atoms terminate the (111) plane Si atom stacks from two ways to one way, and act as the trigger of Frank partial dislocation. The (111) plane stacking sequence abcabc is changed to abcbc with stacking fault and bordered by edge dislocation. The TEM and IFFT (Inverse Fast Fourier Transform) of (111) plane lattice images of SMT defects are obtained to determine the defect type and 30.1.1 IEDM12-697 978-1-4673-4871-3/12/$31.00 ©2012 IEEE