Thermal stability of high-k oxides on SiO
2
/Si
or Si
x
N
y
/SiO
2
/Si for charge-trapping
nonvolatile memories
A. Lamperti,
a
* E. Cianci,
a
O. Salicio,
a
L. Lamagna,
a
S. Spiga
a
and M. Fanciulli
a,b
High dielectric constant (high-k) oxides are foreseen replacement materials in innovative metal–oxide–semiconductor devices
and memory capacitors. In particular, when considering nonvolatile memories, the charge-trapping concept appears to be a
promising solution for flash-type floating gate replacement. Among the high-k oxide properties to be considered, it is
essential to study the compatibility towards the integration of these materials in a complementary metal–oxide–semiconductor
process, in particular to control the stack integrity and any onset of diffusion phenomena upon thermal treatments at tempera-
tures higher than 1000
C. Here, we report on the results obtained from time-of-flight secondary ion mass spectrometry depth
profiling of stacks on the basis of high-k/SiO
2
/Si, integrating HfO
2
, ZrO
2
, or DyScO
x
as charge-trapping layer or high-k/Si
x
N
y
/
SiO
2
/Si integrating DyScO
x
as control (blocking) oxide. The high-k oxides are all grown by atomic layer deposition. We will discuss
the role of the different substrate/oxide coupling in preserving the stack and propose the better combinations in terms of thermal
stability. Copyright © 2012 John Wiley & Sons, Ltd.
Keywords: ToF-SIMS; depth profile; hafnium oxide; zirconium oxide; dysprosium scandate; thermal stability; CMOS compatibility;
charge-trapping memory; high-k
Introduction
For novel emerging metal–oxide–semiconductor devices and
memory capacitors, high dielectric constant (high-k) oxides are
foreseen as candidate replacement materials.
[1–4]
In particular, for
nonvolatile memories, a promising solution for flash-type floating
gate replacement is the charge-trapping structure, which consists
of a TaN/Al
2
O
3
/Si
3
N
4
/SiO
2
/Si (TANOS) multilayered stack.
[5]
The
inclusion of high-k dielectric as charge-trapping (i.e. Si
3
N
4
) or
blocking layer (i.e. Al
2
O
3
) replacement could help in decreasing
the full stack equivalent oxide thickness and, ultimately, further
improve the cell performance in terms of trade-off between
program/erase window and speed and retention. HfO
2
[6,7]
and
ZrO
2
[8–11]
have been successfully integrated as alternative trapping
layer, whereas DyScO
x
[12–15]
has been reported to be a qualified
candidate for the control (blocking) oxide layer. In any case, among
the high-k oxide properties to be considered, the study of the ther-
mal compatibility against the integration of these materials in a
complementary metal–oxide–semiconductor (CMOS) process is
fundamental, particularly the control of the stack integrity, with a
peculiar attention at the interfaces and at onset of diffusion
phenomena upon thermal treatments up to about 1000
C.
[16]
In fact, post-deposition annealing at 900–1000
C is required
for Al
2
O
3
g-phase crystallization; further, 900
C annealing is
also required to grant TaN metal gate crystallization. To
elucidate the above-mentioned properties, the stability of
each layer can be carefully checked by studying the inter-diffusion
of the layers using secondary ion mass spectrometry (SIMS)
depth profiles.
In this work, we make use of the extreme sensitivity of time-of-
flight secondary ion mass spectrometry (ToF-SIMS) to check the
degree of stability in full stacks integrating HfO
2
, ZrO
2
, or DyScO
x
as charge-trapping layer or DyScO
x
as blocking oxide.
Experimental
High-k oxide thin films were grown on SiO
2
/Si or Si
x
N
y
/SiO
2
/Si
(Si
x
N
y
indicating slightly Si-rich Si
3
N
4
) substrates by atomic layer
deposition from metalorganic precursors (TMA, (CpMe)
2
Zr(OMe)
Me, (CpMe)
2
Hf(OMe), Sc(TMHD)
3
, and Dy(TMHD)
3
, for Al, Zr, Hf, Sc,
and Dy, respectively) and H
2
O or O
3
as oxidant gas. N
2
was used
as purging gas between each pulse. The growth temperature was
kept at 300–350
C, to match the required temperature for a
controlled reaction within the atomic layer deposition regime.
Ternary compounds were grown by combining binary atomic
layer deposition processes and varying the pulse ratio during the
growth process.
After deposition, and prior to metal gate integration, stacks
were subjected to rapid thermal annealing (RTA) at different
temperatures, with a peculiar attention to the interval
* Correspondence to: A. Lamperti, Laboratorio MDM, IMM-CNR, Via Olivetti 2,
20864 Agrate Brianza MB, Italy.
E-mail: alessio.lamperti@mdm.imm.cnr.it
a Laboratorio MDM, IMM-CNR, Via Olivetti 2, 20864 Agrate Brianza MB, Italy
b Dipartimento di Scienza dei Materiali, Università di Milano-Bicocca, Milano Italy
Surf. Interface Anal. (2012) Copyright © 2012 John Wiley & Sons, Ltd.
SIMS proceedings paper
Received: 30 September 2011 Revised: 20 April 2012 Accepted: 5 May 2012 Published online in Wiley Online Library
(wileyonlinelibrary.com) DOI 10.1002/sia.5053