IJE TRANSACTIONS B: Applications Vol. 31, No. 5, (May 2018) 752-758 International Journal of Engineering Journal Homepage: www.ije.ir T. Sarkar*, S. Nath Pradhan Department of ECE, National Institute of Technology, Agartala. Agartala, India PAPER INFO Paper history: Received 17 March 2017 Received in revised form 13 January 2018 Accepted 08 March 2018 Keywords: Testing Don’t Care Run Time Leakage Fault Coverage Genetic Algorithm Test Pattern Ordering Pattern Dependency A B S T RA C T Estimating and minimizing the maximum power dissipation during testing is an important task in VLSI circuit realization since the power value affects the reliability of the circuits. Therefore during testing suitable methodologies should be adopted to minimize power consumption. Test patterns generated with –D 1 option of ATALANTA contains don’t care X bits. By suitable filling of don’t cares can minimize the number of switching activity between two successive patterns. The switching power dissipation of the Circuit under Test (CUT) also depends on the order of patterns applied for testing. If consecutive pattern application time is sufficiently large then leakage power dissipation does not alter on the ordering of the patterns. So under this circumstances leakage power does not change but if the pattern application time is small leakage power depends on the ordering of the pattern applied to the CUT. Previous works concern only about don’t care filling or pattern ordering or first filling of don’t care and then ordering for low power circuit testing. Ordering after filling of don’t care may change the benefits of X-filling. The advantage of test power reduction of both the methods - don’t care filling and ordering may be obtained if they are considered together. In this work an approach based on Genetic Algorithm (GA) is used to solve the integrated problem for X-filling and reordering of test patterns considering pattern dependency to minimize the switching activity throughout testing without changing the fault coverage. Effectiveness of the proposed GA based approach compared to existing approach considering test patterns for ISCAS’85 benchmark circuits is shown in the result section. doi: 10.5829/ije.2018.31.05b.10 1. INTRODUCTION 1 Reduction of power consumption at the time of circuit testing becomes a challenging issue as the design consumes more power in test mode compared to functional mode of operation [1]. At present, testing is one of the most vital issues in the development process of an integrated circuit. The issues that depends on testing are manufacturing yield, test cost and product quality [2- 4]. It was shown that test power is much higher than the power consumption in normal functional mode due to several reasons such as (i) Automatic test pattern generation (ATPG) tools generate test patterns that have high toggle rate in order to reduce pattern count and test application time. Therefore the switching activity of the circuit in test mode is often several times higher compared to normal mode of operation. (ii) To reduce *Corresponding Author Email: trupa.sarkar@gmail.com (T. Sarkar) test application time parallel testing is also used, mainly for System-on-Chip (SOC) devices. This parallelism increases power dissipation during test. (iii) The Design- for-Testability (DFT) circuitry is inserted in the circuit under test to improve testing issues. DFT circuit remains idle at normal operation but is used in test mode. These additional active elements further increase power dissipation. In this work single stuck-at fault model is considered. In this fault model the value on the faulty signal line appears to be stuck either at logic ‘0’ or logic ‘1’, referred to as stuck-at-0 or stuck-at-1 respectively. Test patterns are generated using ATALANTA tool. CAD tool- ATALANTA generates test patterns targeting stuck-at fault. Most of the works related to power reduction in the literature describes about dynamic power minimization. But as the technology shrinks down below 65nm leakage power dominates over dynamic power. So, minimizing Test Power Reduction by Simultaneous Do not Care Filling and Ordering of Test Patterns Considering Pattern Dependency Please cite this article as: T. Sarkar, S. Nath Pradhan, Test Power Reduction by Simultaneous Do not Care Filling and Ordering of Test Patterns Considering Pattern Dependency, International Journal of Engineering (IJE), IJE TRANSACTIONS B: Applications Vol. 31, No. 5, (May 2018) 752-758