Radiation Hardened and Leakage Power Atack Resilient 12T SRAM Cell for Secure Nuclear Environments Debabrata Mondal ∗ Indian Institute of Technology Jammu Jammu, Jammu & Kashmir, India 2021PEE1046@iitjammu.ac.in Syed Farah Naz ∗ Indian Institute of Technology Jammu Jammu, Jammu & Kashmir, India 2020REE1022@iitjammu.ac.in Ambika Prasad Shah Indian Institute of Technology Jammu Jammu, Jammu & Kashmir, India ambika.shah@iitjammu.ac.in ABSTRACT Extremely energetic particles prevalent in the nuclear environment make memory cells prone to soft errors. Also, attackers extract secret data of SRAM cells via side-channel attacks (SCAs), and leak- age power analysis attacks (LPAs) are a serious threat to security systems. This research indicates an extremely efective radiation- hardened and LPA-resilient (RHLR12T) SRAM cell that is both radi- ation resistant by design for nuclear applications and LPA-resilient. It ofers better speed, enhanced writing stability and higher overlap percentage compared to other considered SRAM cells, such as 6T, Quatro, We-Quatro, and RHMD10T, utilizing 45nm CMOS technol- ogy at the supply voltage of 1.0V and 27 ◦ C operating temperature. The proposed cell gives 1.141× higher write stability, 1.55× lower write access time, 1.11× increased critical charge and 1.51× better overlap percentage than RHMD10T SRAM cell. ACM Reference Format: Debabrata Mondal, Syed Farah Naz, and Ambika Prasad Shah. 2023. Radi- ation Hardened and Leakage Power Attack Resilient 12T SRAM Cell for Secure Nuclear Environments. In Proceedings of the Great Lakes Symposium on VLSI 2023 (GLSVLSI ’23), June 5–7, 2023, Knoxville, TN, USA. ACM, New York, NY, USA, 2 pages. https://doi.org/10.1145/3583781.3590321 1 INTRODUCTION In today’s modern world, SRAM is widely employed as a memory element in the controller of severe nuclear systems. This memory el- ement is exposed to a high radiation environment where extremely energetic particles strike the sensitive node of the memory element that fips the data stored in it. This phenomenon is known as soft error. Furthermore, as semiconductor technology advances, transis- tor size is increasingly reduced, making the memory element more vulnerable to soft errors because the critical charge of the memory element reduces when transistor size is reduced [1]. Several outstanding SRAM cells based on circuit-level redun- dancy to provide radiation tolerance ability have recently been described. Jahinuzzaman et al. in [2] suggested Quatro-10T soft error tolerant SRAM cell with four nodes and restores two comple- mentary data pairs. But it cannot restore every single event upsets and has the disadvantage of poor writability, and sufers from a major writing failure at high voltages and frequency. To cover up ∗ Both authors contributed equally to this research. Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for proft or commercial advantage and that copies bear this notice and the full citation on the frst page. Copyrights for third-party components of this work must be honored. For all other uses, contact the owner/author(s). GLSVLSI ’23, June 5–7, 2023, Knoxville, TN, USA © 2023 Copyright held by the owner/author(s). ACM ISBN 979-8-4007-0125-2/23/06. https://doi.org/10.1145/3583781.3590321 the disadvantage, L. Dang et al. in [3] suggested We-Quatro 12T SRAM cell with added two extra NMOS transistors so that the strength of access transistors is increased; thus, it does not sufer from writability failure conditions. S. Pal et al. in [1] suggested RHMD10T SRAM, which has the highest read stability and better critical charge while consuming low power. Still, it sufers from longer write delay and lower write ability. Additionally, attacks on key storage and retrieval are possible using software and physical approaches that can successfully read data from SRAM chips via SCAs [4]. LPA has become a serious issue to cryptographic systems as far as the security of data is concerned [5]. It can be utilized to disclose crucial information about mem- ory through its leakage power consumption, which has therefore emerged as a major threat to the security of cryptographic modules used in nuclear systems [5]. A similar approach has been followed by the authors in [6] wherein two additional OFF state NMOS tran- sistors are added in conventional 6T SRAM, thus equalising the leakage current components and making the design LPA resilient. 2 PROPOSED RHLR12T SRAM CELL AND PERFORMANCE COMPARISON In RHMD10T SRAM cell [1], we observed that when storage node (Q) stores ‘0’, the total number of transistors through which leakage current is fowing is 3, and when Q stores ‘1’, the total leakage current components are 7. Thus the mismatch in the total number of leakage current components and leakage power analysis leads to the easy depiction of the data stored in the cell by the attacker. Therefore, we have added two additional NMOS transistors (N5 and N6) in the RHMD10T SRAM cell as shown in Fig. 1 (a) so that the total number of leakage current components gets equalized for both the cases when Q stores ‘0’ and ‘1’. The stability and access time of all the SRAM cells with supply variation is shown in Fig. 2 (a)-(e). Various performance parameters for all the considered SRAM cells are listed in Table 1, and the best among all are highlighted for all the considered parameters. Results indicate that the proposed cell is performing well in most of the parameters with some area overhead. This is because the additional access transistors N5 and N6 increase the strength of access transis- tors, which improves write stability and also lowers write delay. So, the proposed SRAM cell provides better write stability and lower write delay than all the considered SRAM cells. For the soft error robustness analysis, we have used a double exponential current pulse to model the transient pulse produced by SEU. From Fig. 1(b), it is observed that the Q crit increases with supply voltage and decreases with temperature for both RHMD10T and proposed SRAM cells, and for each case, the proposed design 227