Gyancity Journal of Engineering and Technology, Vol.2, No.1, pp. 62-69, January 2016 ISSN: 2456-0065 DOI: 10.21058/gjet.2016.2107 62 Clock Gating Based Low Power Energy Efficient Gurmukhi Unicode Reader Design on FPGA Sunny Singh, Amanpreet Kaur School of Computer Sciences Chitkara University, Rajpura, India Er.singhsunny2207@gmail.com Abstract— In the domain of High Performance Energy Efficient Computing (HPEEC), the focus of research is shifting toward energy efficient computing or low power VLSI design or green computing. We are applying three different clock gating technique in target design of Gurmukhi Unicode Reader (GUR). These power saving techniques reduce the power dissipation of GUR in significant amount. It has been observed that if we switch to flip flop based clock gating instead of simple clock then we can save 89.6% of clock power and we can save 90.48% of clock power if we switch to latch free clock gating (LFCG) or latch based clock gating (LBCG) in case of all SSTL based logic families. It has been observed that if we switch to flip flop based clock gating instead of simple clock then we can save 23.88% of IO power and we can save 26.59% of IO power if we switch to either LFCG or LBCG in case of SSTL2_II_DCI. It has been observed that if we switch to FFBCG instead of simple clock then we can save 52.38% of total power and we can save 56.67% of total power if we switch to either LFCG or LBCG in case of SSTL2_II_DCI. Index Terms— Low Power, Energy Efficient, Gurmukhi Unicode, FPGA, SSTL. 1. Introduction Clock gating is an energy efficient technique. It is used for power savings by gating off the functional units not required by the currently executing instruction, as determined by the Instruction Decoder unit [1]. Figure 1: Principles of Clock Gating f (CG) CLK CLKG