2240 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 27, NO. 13, JULY 1, 2009 All-Optical Binary Pattern Recognition at 42 Gb/s Roderick Peter Webb, Xuelin Yang, Member, IEEE, Robert J. Manning, Member, IEEE, Graeme D. Maxwell, Alistair J. Poustie, Member, IEEE, Sebastien Lardenois, Member, IEEE, and David Cotter Abstract—In this paper, a programmable binary pattern recog- nition system that also indicates the temporal position of the matched target sequence is described. The system employs all-op- tical logic gates, and the number of gates required by the system is independent of the length of the target bit sequence. Experimental results with 42.6 Gb/s input data and target patterns up to 256 bits in length are presented. Index Terms—Integrated optics, optical logic devices, optical planar waveguides, semiconductor optical amplifiers. I. INTRODUCTION A S optical transmission system bit rates increase and espe- cially as packet-switched networks are introduced, all-op- tical pattern recognition at the line rate will find many appli- cations in future telecommunications systems. These include address and port number recognition, not only for the purpose of routing but also for data security applications. One example is the photonic firewall being developed by the European FP6 project WISDOM [1], which will use high-speed ( 40 Gb/s) pattern recognition with semiconductor optical amplifier (SOA) based all-optical gates as part of the initial screening of in- coming packets. By implementing the first level of packet fil- tering in the optical layer, the burden on the subsequent elec- tronic and software layers will be substantially reduced. With low-speed data, optical pattern recognition may be car- ried out by a bit-serial circuit comprising a small number of optical logic gates (Fig. 1). The target binary sequence is gen- erated in synchronism with the data to be searched and com- pared with it bit by bit. Successive bit-matching results are com- bined by an AND gate with a 1-bit period delayed feedback. But, as the data rate is increased, it becomes more difficult to make the physical length of the optical feedback loop suffi- ciently short. In a 40 Gb/s system, the loop length would have to be 25 ps, whereas, even in an SOA-based gate—the most compact type of optical gate—the propagation time through the Manuscript received May 02, 2008; revised September 10, 2008. First pub- lished April 17, 2009; current version published June 26, 2009. This work was supported by the Science Foundation Ireland grant 06/IN/I969 and by the European Union project WISDOM. R. P. Webb, R. J. Manning, and D. Cotter are with the Tyndall National Insti- tute and Department of Physics, University College Cork, Cork, Ireland(e-mail: rod.webb@tyndall.ie; bob.manning@tyndall.ie; david.cotter@tyndall.ie). X. Yang is now with theSchool of Electrical Engineering, Bangor University Dean Street, Bangor, LL57 1UT, U.K.(e-mail: ees818@bangor.ac.uk). G. D. Maxwell, A. J. Poustie, and S. Lardenois are with the Centre for Integrated Photonics (CIP) Ltd, Ipswich IP5 3RE, U.K. (e-mail: Graeme.Maxwell@ciphotonics.com; Alistair.Poustie@ciphotonics.com; Sebastien.Lardenois@ciphotonics.com). Color versions of one or more of figures in this paper are available at http:// ieeexplore.ieee.org. Digital Object Identifier 10.1109/JLT.2008.2006067 Fig. 1. Bit-serial pattern recognition system. The short feedback loop is only feasible with low-speed data. Fig. 2. Schematic of the pattern recognition system. SOA alone would be 10–30 ps. This constraint is normally over- come through the use of parallel or pipelined circuits, which have been demonstrated for address recognition [2], [3]. How- ever, these architectures require at least one gate per target pat- tern bit. The length of target is therefore restricted by both the practicable level of integration and the acceptable power con- sumption. Analog address recognition techniques based on cor- relation can also be used, especially with phase-encoded signals [4]–[6]. These schemes either restrict the data to a set of code words with low cross-correlation coefficients or rely on accu- rately thresholding the output. The thresholding tolerance be- comes more severe as the number of bits correlated increases, again restricting the length of the target pattern. In order to overcome these limitations, we have proposed a novel digital system for recognition of patterns in high-speed return-to-zero formatted data that has a low gate count for any length of target, requires only a low-speed target input, and does not need bit-level synchronization [7]. The position of each oc- currence of the target bit sequence in the selected data segment is located temporally, enabling the system to be also used for synchronization pulse generation. In this paper, we review the operating principle and features of the system and present ex- perimental results using 42.6 Gb/s input data and target binary patterns from 8 to 256 bits in length. 0733-8724/$25.00 © 2009 IEEE