This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY 1 Reliability of Copper Through-Package Vias in Bare Glass Interposers Kaya Demir, Andac Armutlulu, Venky Sundaram, P. Markondeya Raj, and Rao R. Tummala, Fellow, IEEE Abstract— Thermomechanical reliability of copper-plated through-package vias (TPVs) in ultrathin bare glass interposers was investigated through modeling, design, fabrication, reliability characterization, and failure analysis. Finite-element models were developed to analyze stress and strain distribution in TPV structures, and to obtain design guidelines for reliable TPVs. In order to experimentally validate the predictions of simulations, bare glass substrates of 100 μm thickness with vias of 30 μm diameter at 120 μm pitch were metallized using Ti/Cu sputtering, followed by patterning and electroplating. Cu TPV daisy chains were fabricated and subjected to thermal cycling test between -55 °C and 125 °C to assess their thermomechanical reliability. Detailed cross-sectional analysis was also carried out by scanning electron microscope imaging of TPV cross sections. No electrical failures were detected in the Cu TPV chains. Failure analysis revealed copper delamination and crack formation in glass. The experimental reliability results are consistent with the thermomechanical models. Design and process recommendations are provided based on the modeling and experimental results. Index Terms— Failure mechanism analysis, finite-element modeling (FEM), glass interposer, reliability, through-package vias (TPVs). I. I NTRODUCTION T HE increasing demand for memory-to-logic bandwidth for both mobile and high-performance applications has been driving continual evolution in electronics packaging from traditional 2-D multichip packages to 3-D packages [1]. To achieve such vertical integration at low cost, low power, and high performance, 2.5-D and 3-D interposers, as illustrated in Fig. 1, have been proposed as a compelling alternative to 3-D IC stacks with through-silicon vias (TSVs) in logic and memory [2]. These ultrathin interposers can facilitate short and high-density vertical interconnections between logic and memory to achieve high bandwidth. However, the inter- poser material is required to have ideal electrical, thermal, mechanical properties, and low-cost manufacturing processes for ultrasmall through-package via (TPV) formation. As an interposer substrate material, organic laminates are commonly preferred because of their low cost and compati- bility with existing manufacturing infrastructure [2]. However, the primary disadvantage of organic interposers arises from their limited fine-pitch I/O capability due to three reasons: 1) dimensional instability; 2) high CTE; and 3) high warpage Manuscript received October 3, 2016; revised January 26, 2017; accepted March 4, 2017. Recommended for publication by Associate Editor H.-C. Cheng upon evaluation of reviewers’ comments. (Corresponding author: Kaya Demir.) K. Demir, V. Sundaram, P. M. Raj, and R. R. Tummala are with the Packaging Research Center, Georgia Institute of Technology, Atlanta, GA 30332 USA (e-mail: kaya@gatech.edu). A. Armutlulu is with ETH Zurich, 8092 Zurich, Switzerland. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCPMT.2017.2691407 Fig. 1. Cross-section schematic of proposed (a) 2.5-D and (b) 3-D interposer packages. during assembly [3]. To mitigate these shortcomings of organic interposers, silicon interposers are being developed and fab- ricated with standard back-end-of-line wafer processes to achieve required wiring and I/O density [4]–[6]. However, dis- advantages of silicon interposers are: 1) expensive fabrication processes, and 2) high electrical loss in RF domain due to the semiconducting silicon. To address the disadvantages of organic and silicon inter- posers, glass is proposed as an alternative substrate mate- rial due to its: 1) superior mechanical properties of glass compared to organic laminates, and 2) lower material cost and electrical loss compared to silicon [7]. Previous studies demonstrated superior electrical performance of RF passives, integrated RF modules, and high-bandwidth 2.5-D interposers with large-area panel-based glass interposers offering cost benefits [8]–[11]. In spite of these advances, reliability of copper-plated TPV in glass faces two key challenges: 1) brittleness of glass, whose strength further reduces in contact with water [12], [13] and by formation of defects during handling and via formation, and 2) high coefficient of thermal expansion (CTE) mismatch between glass (3 ppm/K) and copper (17 ppm/K), leading to thermomechanical stresses that can cause crack propagation in glass, interfacial delamination of copper and glass, and plastic deformation in copper. Therefore, there is a compelling need to study TPV reliability to develop design guidelines to achieve reliable TPV structures. Polymer lamination on glass is being pursued as a solution to address challenges with glass handling and metallization [14]. Low-modulus polymer has at least five purposes: 1) control glass damage during handling; 2) inhibit moisture contact to glass; 3) filling ultrasmall defects on glass surfaces to increase its strength; 4) act as a buffer layer 2156-3950 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.