Electrical Characterization and Design Optimization of Embedded Chip in Substrate Cavities Nithya Sankaran, Baik-Woo Lee, Venky Sundaram, Ege Engin, Mahadevan Iyer, Madhavan Swaminathan and Rao Tummala Packaging Research Center School of Electrical and Computer Engineering, Georgia Institute of Technology 813 Ferst Drive, Atlanta, GA 30332-0560, USA Email - gth874e(mail.gatech.edu, Phone: (404) 694 -1788 Abstract Endless demands for digital convergence by ultra- miniaturization, increased functionality, better performance and low cost in both mobile and desktop systems are driving the needs for new and unique solutions in system integration. The requirements of future electronic systems include faster, smaller, lighter and thinner products. Advanced electronic packaging caters to these ultra-miniaturization and performance needs. The approach of embedding passive components has been in the fray for a while now and the relatively newer perspective to sustain the miniaturization trend efficiently is by embedded active chips as well. This paper discusses the electrical design aspects of embedded actives dealing with the chip-last methodology of embedding dies in particular. The various issues that are expected to surface are made clear through electromagnetic simulations using 3D solver tools. The transmission lines forming the substrate wiring when the cavities are made are analyzed comprehensively. A test vehicle is fabricated based on this new approach and preliminary measurement results are also included in this paper. 1. Introduction System-in-Package (SIP) and System-On-Package (SOP) are key enabling technologies for digital and RF micro miniaturization and system integrations on silicon, ceramic and organic substrate platforms, offering diverse functionality in a single module. There is also a continuing demand for the miniaturization of this module [1]. The 3D integration and stacking of components are also methods that are applied to achieve the miniaturization of systems. [2]. One of the innovative approaches adopted to achieve this 3D integration is embedding active and passive components. Embedded chip technology is being accepted for miniaturization of RF, base band and other mixed signal modules. The trend of embedding active chips in substrates has been initiated by General Electric Co [3], Intel [4], Shinko [5], Fraunhofer Institute [6] and others. Embedded actives are sought after as they are expected to reduce the parasitic effects of interconnects (reduced interconnect length) resulting in lower power dissipation, provide better electromagnetic shielding. They also offer smaller and thinner package profiles. The Embedded actives can be broadly classified into Chip first and Chip last approaches. In the Chip First approach, the wiring and build-up layers are formed above the chip. This approach suffers from the following limitations: (1) The chip, once it is embedded is subjected to a whole lot of processing steps and it can be affected due to the fabrication (2) Serial chip-to- build-up processes accumulate yield losses associated with each process. (3) Defective chips cannot be easily reworked in current embedded package structure. This needs 100% KGDs (Known Good Die). (4) The interconnections in chip-first approach which are direct metallurgical contacts can encounter fatigue failures due to thermal stress. (5) Thermal management issues are also evident since the chip is totally embedded within polymer materials of substrate or build-up layers processes. In the Chip Last approach the chip is placed in a cavity after all the wiring and build-up layers have been completed. This method is to almost relieve all the stresses of the fabrication that chip is put through in the earlier case. The final component to go in the system package is the die. Most of the published works on embedded actives are mainly from materials and process technology perspective. Electrical analysis of the embedded active technologies has not been well reported and documented to date. This paper gives insight into the issues likely to be faced in the electrical front when the chip last methodology of embedding dies is being followed and also on the ways that can be sought to improve the performance. A comparison with Chip first approach is also done in this study. This is to show that the problems of impedance variation and matching also surface in the substrate wiring of the Chip-first case. 2. Embedded Chip Cavity Designs The transmission lines determine signal propagation characteristics in a package and the behavior of these when resorting to SIP/SOP with embedded chips needs special attention. Primarily this analysis includes investigation of lines inside the cavities, buried transmission lines, the transition of surface micro strip lines to buried lines, the proximity of the transmission lines to the dielectric cavity wall, and the influence of the cavity sizes. This includes a parametric study to show what kind of variations one can expect when adopting embedded actives and also to quantify how much of variation the system requirements can tolerate and if it is feasible to adapt to this new method of packaging. Trace withiii the cavity Trace oin the stibstirate stiiifa ce b a - cavity deptl b - ikt of suib ste below the tace Fig 1. Cross-section of substrate with Cavity 992 2007 Electronic Components and Technology Conference 1-4244-0985-3/07/$25.00 02007 IEEE